WM8281 Datasheet, PDF (301/392 Pages) Cirrus Logic – Low Power Audio System with Ambient Noise Cancellation and Echo Cancellation

Rev 4.0
WM8281
REGISTER BIT
ADDRESS
LABEL
DEFAULT
DESCRIPTION
R23
(0017h)
Write
Sequencer
Ctrl 1
9 WSEQ_BUSY
(read only)
8:0 WSEQ_CURREN
T_INDEX [8:0]
(read only)
0
000h
Sequencer Busy flag (Read Only).
0 = Sequencer idle
1 = Sequencer busy
Sequence Current Index. This indicates
the memory location of the most recently
accessed command in the write
sequencer memory.
Coding is the same as
WSEQ_START_INDEX.
Table 121 Write Sequencer Control - Status Readback
The Write Sequencer status is an input to the Interrupt control circuit and can be used to trigger an
Interrupt event - see “Interrupts”.
The Write Sequencer status can be output directly on a GPIO pin as an external indication of the
Write Sequencer. See “General Purpose Input / Output” to configure a GPIO pin for this function.
PROGRAMMING A SEQUENCE
A Control Write Sequence comprises a series of write operations to data bits (or groups of bits) within
the control register map. Each write operation is defined by a block of 2 registers, each containing 5
fields, as described below.
The block of 2 registers is replicated 510 times, defining each of the sequencer’s 510 possible index
addresses. Many sequences can be stored in the sequencer memory at the same time, with each
assigned a unique range of index addresses.
The WSEQ_DELAYn register is used to identify the ‘end of sequence’ position, as described below.
Note that, in the following descriptions, the term ‘n’ denotes the sequencer index address (valid from 0
to 509).
WSEQ_DATA_WIDTHn is a 3-bit field which identifies the width of the data block to be written. Note
that the maximum value of this field selects a width of 8-bits; writing to register fields greater than 8
bits wide must be performed using two separate operations of the Write Sequencer.
WSEQ_ADDRn is a 13-bit field containing the register address in which the data should be written.
WSEQ_DELAYn is a 4-bit field which controls the waiting time between the current step and the next
step in the sequence (ie. the delay occurs after the write in which it was called). The total delay time
per step (including execution) is defined below, giving a useful range of execution/delay times from
3.3s up to 1s per step. Setting this field to 0xF identifies the step as the last in the sequence.
If WSEQ_DELAYn = 0h or Fh, the step execution time is 3.3µs
For all other values, the step execution time is 61.44µs x ((2 ^WSEQ_DELAY ) - 1)
WSEQ_DATA_STARTn is a 4-bit field which identifies the LSB position within the selected control
register to which the data should be written. For example, setting WSEQ_DATA_STARTn = 0100 will
select bit 4 as the LSB position of the data to be written.
WSEQ_DATAn is an 8-bit field which contains the data to be written to the selected control register.
The WSEQ_DATA_WIDTHn field determines how many of these bits are written to the selected
control register; the most significant bits (above the number indicated by WSEQ_DATA_WIDTHn) are
ignored.
The register definitions for Step 0 are described in Table 122. The equivalent definitions also apply to
Step 1 through to Step 509, in the subsequent register address locations.
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