CS3318 Datasheet, PDF (35/44 Pages) Cirrus Logic – 8-Channel Analog Volume Control

7.5.2
CS3318
Zero-Crossing Mode (Bits 1:0)
Default = 01
Function:
These bits control the Zero-Crossing detection mode as shown in Table 9. Refer to the “Zero-Cross-
ing Modes” section on page 22 for more information.
ZCMode[1:0]
Zero-Crossing Mode
00
Volume changes take effect immediately.
01
Volume changes take effect on a signal zero-crossing. If a zero-crossing is not detected
before the period specified by the TimeOut[2:0] bits has elapsed, the volume change will be
implemented immediately when the time-out period elapses. If the volume setting is
changed again before the original volume change has been implemented, the original
change will be discarded, the time-out period will be reset, and the new volume setting will
take effect when a zero-crossing is detected or the time-out period elapses.
10
Volume changes take effect on a signal zero-crossing. If a zero-crossing is not detected
before the period specified by the TimeOut[2:0] bits has elapsed, the volume change will be
implemented immediately when the time-out period elapses. If the volume setting is
changed again before the original volume change has been implemented, the original vol-
ume change will be implemented immediately upon reception of the new volume change
command, the time-out period will be reset, and the new volume setting will take effect when
a zero-crossing is detected or the time-out period elapses.
11
Reserved
Table 9. Zero-Crossing Mode Settings
7.6 Channel Power - Address 0Dh
7
PDN8
6
PDN7
5
PDN6
4
PDN5
3
PDN4
2
PDN3
1
PDN2
0
PDN1
7.6.1
Power Down Channel X (Bit 0 - 7)
Default = 0
Function:
Each respective channel will enter a low-power state whenever this bit is set. A channel’s power-down
bit must be cleared for normal operation to occur.
7.7 Master Power - Address 0Eh
7
Reserved
6
Reserved
5
Reserved
4
Reserved
3
Reserved
2
Reserved
1
Reserved
0
PDN_ALL
7.7.1
Power Down All (Bit 0)
Default = 1
Function:
The device will enter a low-power state whenever this bit is set. The power-down bit is set by default
and must be cleared before normal operation can occur. The control registers remain accessible, and
their contents are retained while the device is in power-down.
DS693F1
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