CS3318 Datasheet, PDF (11/44 Pages) Cirrus Logic – 8-Channel Analog Volume Control

CS3318
CONTROL PORT SWITCHING CHARACTERISTICS - SPI™ FORMAT
(Inputs: Logic 0 = DGND, Logic 1 = VD, C_L = 20 pF)
Parameter
CCLK Clock Frequency
RESET Rising Edge to CS Falling
CS High Time Between Transmissions
CS Falling to CCLK Edge
CCLK Low Time
CCLK High Time
CDIN to CCLK Rising Setup Time
CCLK Rising to DATA Hold Time
Rise Time of CCLK and CDIN
Fall Time of CCLK and CDIN
(Note 8)
(Note 9)
(Note 9)
Symbol
f_sck
t_srs
t_csh
t_css
t_scl
t_sch
t_dsu
t_dh
t_r2
t_f2
Min
0
100
1.0
20
66
66
40
15
-
-
Max
6.0
-
-
-
-
-
-
-
100
100
Unit
MHz
ns
μs
ns
ns
ns
ns
ns
ns
ns
8. Data must be held for sufficient time to bridge the transition time of CCLK.
9. For f_sck <1 MHz.
RESET
t _srs
CS
t _css
CCLK
t _scl t _sch
t _csh
t _r2
t _f2
MOSI
t _dsu
t _dh
Figure 2. Control Port Timing - SPI Format
DS693F1
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