CS3318 Datasheet, PDF (25/44 Pages) Cirrus Logic – 8-Channel Analog Volume Control

CS3318
input of device N+1 may be repeated for up to 128 devices per single CS signal. If more than 128 devices
are required in a system, separate CS signals may be used to create additional chains of up to 128 devices
per CS signal.
As each device is placed into reset (RESET is low), its ENOut signal is driven low. The ENOut signal will
continue to be driven low until the device is taken out of reset (RESET is high) and the Enable bit (see “En-
able Next Device (Bit 0)” on page 41) is set, at which time the ENOut signal will be driven high.
To configure a unique Individual device address for each device on the shared serial bus, the first device
must be reset (a low to high transition on its RESET pin), the Individual device address register must be
written (using the CS3318’s default device address) with a unique device address, and the Enable bit must
be set to take the next device in the serial control chain out of reset. This process may be repeated until all
devices in the serial control chain have been assigned a new Individual device address. Figure 10 dia-
grams this configuration process.
Start
This loop steps through the
devices in a chain, setting a
unique Individual chip adress
for each device as it
progresses.
Apply System Power
Reset the First Device
in the Chain
Using the default chip address,
perform a write cycle to change the
Individual chip address register to a
unique value.
Optionally, device configuration (initial
volume settings, Group addresses,
etc.) may be implemented using the
new Individual device address.
At this point, the chip addresses of each
device are set to their default value. The
ENout pin on each device is low, holding
each subsequent device in a reset state.
From this point forward, the device will only
respond to register reads and writes when
addressed with this new Individual device address.
A device will also respond to register writes when
addressed with its Group 1 or Group 2 address.
Using the new Individual chip address, _No
perform a write cycle to set the Enable
bit.
Have all the devices in the
chain been assigned a unique
chip address?
Each device may now be
Yes independently adressed through the
serial bus using the device's assigned
unique chip address.
This will cause the device's
ENout pin to be driven high,
bringing the next device in the
chain out of its reset state.
The Reset input pins of all devices in the chain are
now high. The serial control interface will
communicate with each device in parallel, but each
device will only respond when the first byte clocked
in on the serial control bus matches its Individual,
Group 1 or Group 2 address. If the first byte
clocked in does not match the one of the device's
chip addresses, the device will ignore all
subsequent traffic on the bus until a new
communication cycle is initiated.
Figure 10. Individual Device Address Configuration Process
Notice that Figure 10 shows the setting of the Individual address and the setting of the Enable bit as two
discrete steps. While this demonstrates one approach to device configuration, it should be noted that two
steps are not necessary to complete the action of setting the Individual address and enabling the next de-
vice. This may be done simultaneously with one register write (containing the new Individual address and
the Enable bit set) to the Individual address register.
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