CS4351 Datasheet, PDF (28/41 Pages) Cirrus Logic – 192 kHz STEREO DAC WITH 2 Vrms LINE OUT

CS4351
6. REGISTER DESCRIPTION
** All register access is R/W unless specified otherwise**
6.1 Chip ID - Register 01h
7
PART4
1
6
PART3
1
5
PART2
1
4
PART1
1
3
PART0
1
2
REV2
-
1
REV1
-
0
REV0
-
Function:
This register is Read-Only. Bits 7 through 3 are the part number ID which is 11111b and the remaining
Bits (2 through 0) are for the chip revision (Rev. A = 000, Rev. B = 001, ...)
6.2 Mode Control 1 - Register 02h
7
6
5
4
3
2
1
0
Reserved
DIF2
DIF1
DIF0
DEM1
DEM0
FM1
FM0
0
0
0
0
0
0
0
0
6.2.1 DIGITAL INTERFACE FORMAT (DIF2:0) BITS 6-4
Function:
These bits select the interface format for the serial audio input.
The required relationship between the Left/Right clock, serial clock and serial data is defined by the Digital
Interface Format and the options are detailed in Figures 5-7.
DIF2
0
0
0
0
1
1
1
1
DIF1
0
0
1
1
0
0
1
1
DIF0
0
1
0
1
0
1
0
1
DESCRIPTION
Left Justified, up to 24-bit data
I²S, up to 24-bit data
Right Justified, 16-bit data
Right Justified, 24-bit data
Right Justified, 20-bit data
Right Justified, 18-bit data
Reserved
Reserved
Table 8. Digital Interface Formats
Format
0 (Default)
1
2
3
4
5
FIGURE
5
6
7
7
7
7
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DS566PP2