CS4351 Datasheet, PDF (20/41 Pages) Cirrus Logic – 192 kHz STEREO DAC WITH 2 Vrms LINE OUT

CS4351
4.5 Recommended Power-up Sequence
4.5.1 Stand-Alone Mode
1. Hold RST low until the power supplies and configuration pins are stable, and the master and
left/right clocks are locked to the appropriate frequencies, as discussed in section 4.2. In this state,
the control port is reset to its default settings, VQ will remain low, and VBIAS will be connected
to VA.
2. Bring RST high. The device will remain in a low power state with VQ low and will initiate the
Stand-Alone power-up sequence after approximately 512 LRCK cycles in Single-Speed Mode
(1024 LRCK cycles in Double-Speed Mode, and 2048 LRCK cycles in Quad-Speed Mode).
4.5.2 Control Port Mode
1. Hold RST low until the power supply is stable, and the master and left/right clocks are locked to
the appropriate frequencies, as discussed in section 4.2. In this state, the control port is reset to its
default settings, VQ will remain low, and VBIAS will be connected to VA.
2. Bring RST high. The device will remain in a low power state with VQ low.
3. Perform a control port write to the CP_EN bit prior to the completion of approximately 512
LRCK cycles in Single-Speed Mode (1024 LRCK cycles in Double-Speed Mode, and 2048 LRCK
cycles in Quad-Speed Mode). The desired register settings can be loaded while keeping the PDN
bit set to 1.
4. Set the PDN bit to 0. This will initiate the power-up sequence, which lasts approximately 50 µs
when the POPG bit is set to 0. If the POPG bit is set to 1, see Section 4.6 for a complete description
of power-up timing.
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DS566PP2