CS4351 Datasheet, PDF (21/41 Pages) Cirrus Logic – 192 kHz STEREO DAC WITH 2 Vrms LINE OUT

CS4351
4.6 Popguard^® Transient Control
The CS4351 uses a novel technique to minimize the effects of output transients during power-up and pow-
er-down. This technology, when used with external DC-blocking capacitors in series with the audio out-
puts, minimizes the audio transients commonly produced by single-ended single-supply converters. It is
activated inside the DAC when the RST pin is toggled and requires no other external control, aside from
choosing the appropriate DC-blocking capacitors.
4.6.1 Power-up
When the device is initially powered-up, the audio outputs, AOUTA and AOUTB, are clamped to
GND. Following a delay of approximately 1000 sample periods, each output begins to ramp toward
the quiescent voltage. Approximately 10,000 LRCK cycles later, the outputs reach V_Q and audio
output begins. This gradual voltage ramping allows time for the external DC-blocking capacitors
to charge to the quiescent voltage, minimizing audible power-up transients.
4.6.2 Power-down
To prevent audible transients at power-down, the device must first enter its power-down state.
When this occurs, audio output ceases and the internal output buffers are disconnected from AOU-
TA and AOUTB. In their place, a soft-start current sink is substituted which allows the DC-block-
ing capacitors to slowly discharge. Once this charge is dissipated, the power to the device may be
turned off and the system is ready for the next power-on.
4.6.3 Discharge Time
To prevent an audio transient at the next power-on, the DC-blocking capacitors must fully dis-
charge before turning on the power or exiting the power-down state. If full discharge does not oc-
cur, a transient will occur when the audio outputs are initially clamped to GND. The time that the
device must remain in the power-down state is related to the value of the DC-blocking capacitance
and the output load. For example, with a 3.3 µF capacitor, the minimum power-down time will be
approximately 0.4 seconds.
4.7 Mute Control
The Mute Control pins go active during power-up initialization, reset, muting (see section 6.4.3), or if the
MCLK to LRCK ratio is incorrect. These pins are intended to be used as control for external mute circuits
to prevent the clicks and pops that can occur in any single-ended single supply system.
Use of the Mute Control function is not mandatory but recommended for designs requiring the absolute
minimum in extraneous clicks and pops. Also, use of the Mute Control function can enable the system de-
signer to achieve idle channel noise/signal-to-noise ratios which are only limited by the external mute cir-
cuit. Please see “Typical Connection Diagram” on page 15 for a suggested mute circuit for single supply
systems. This FET circuit must be placed in series after the RC filter, otherwise noise may occur during
muting conditions. Further ESD protection will need to be taken into consideration for the FET used. If
dual supplies are available, the BJT mute circuit from Figure 12 in the CS4398 datasheet (active Low) may
be used.
DS566PP2
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