CS4351 Datasheet, PDF (17/41 Pages) Cirrus Logic – 192 kHz STEREO DAC WITH 2 Vrms LINE OUT

CS4351
4.2 System Clocking
The device requires external generation of the master (MCLK), left/right (LRCK) and serial (SCLK)
clocks. The left/right clock, defined also as the input sample rate (F_s), must be synchronously derived from
the MCLK according to specified ratios. The specified ratios of MCLK to LRCK, along with several stan-
dard audio sample rates and the required MCLK frequency, are illustrated in Tables 4-6.
Refer to section 4.3 for the required SCLK timing associated with the selected Digital Interface Format,
and SWITCHING SPECIFICATIONS - SERIAL AUDIO INTERFACE, page 11 for the maximum allowed
clock frequencies.
Sample Rate
(kHz)
32
44.1
48
Sample Rate
(kHz)
64
88.2
96
Sample Rate
(kHz)
176.4
192
256x
8.1920
11.2896
12.2880
384x
12.2880
16.9344
18.4320
MCLK (MHz)
512x
768x
16.3840
24.5760
22.5792
33.8688
24.5760
36.8640
1024x
32.7680
45.1584
49.1520
Table 4. Single-Speed Mode Standard Frequencies
1152x
36.8640
MCLK (MHz)
128x
192x
256x
384x
8.1920
12.2880
16.3840
24.5760
11.2896
16.9344
22.5792
33.8688
12.2880
18.4320
24.5760
36.8640
Table 5. Double-Speed Mode Standard Frequencies
512x
32.7680
45.1584
49.1520
64x
11.2896
12.2880
96x
16.9344
18.4320
MCLK (MHz)
128x
22.5792
24.5760
192x
33.8688
36.8640
Table 6. Quad-Speed Mode Standard Frequencies
= Denotes clock modes which are NOT auto detected
256x
45.1584
49.1520
DS566PP2
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