CS4351 Datasheet, PDF (18/41 Pages) Cirrus Logic – 192 kHz STEREO DAC WITH 2 Vrms LINE OUT

CS4351
4.3 Digital Interface Format
The device will accept audio samples in 1 of 4 digital interface formats in Stand-Alone mode, as illustrated
in Table 7, and 1 of 6 formats in Control Port mode, as illustrated in Table 8.
4.3.1 Stand-Alone Mode
The desired format is selected via the DIF1 and DIF0 pins. For an illustration of the required rela-
tionship between the LRCK, SCLK and SDIN, see Figures 5-7. For all formats, SDIN is valid on
the rising edge of SCLK. Also, SCLK must have at least 32 cycles per LRCK period in format 2,
and 48 cycles per LRCK period in format 3.
DIF0
0
0
1
1
DIF1
DESCRIPTION
0 I²S, up to 24-bit Data
1 Left Justified, up to 24-bit Data
0 Right Justified, 24-bit Data
1 Right Justified, 16-bit Data
FORMAT
0
1
2
3
FIGURE
6
5
7
7
Table 7. Digital Interface Format - Stand-Alone Mode
4.3.2 Control Port Mode
The desired format is selected via the DIF2, DIF1 and DIF0 bits in the Mode Control 2 register (see
section 6.2.1) . For an illustration of the required relationship between LRCK, SCLK and SDIN,
see Figures 5-7. For all formats, SDIN is valid on the rising edge of SCLK. Also, SCLK must have
at least 32 cycles per LRCK period in format 2, 48 cycles in format 3, 40 cycles in format 4, and
36 cycles in format 5.
LRCK
Left Channel
Right Channel
SCLK
SDIN
MSB -1 -2 -3 -4 -5
+5 +4 +3 +2 +1 LSB
MSB -1 -2 -3 -4
+5 +4 +3 +2 +1 LSB
Figure 5. Left Justified up to 24-Bit Data
LRCK
SCLK
SDIN
Left Channel
Right Channel
MSB -1 -2 -3 -4 -5
+5 +4 +3 +2 +1 LSB
MSB -1 -2 -3 -4
Figure 6. I²S, up to 24-Bit Data
+5 +4 +3 +2 +1 LSB
LRCK
SCLK
Left Channel
R ight Cha nnel
SDIN MSB
MSB +1 +2 +3 +4 +5
-7 -6 -5 -4 -3 -2 -1 LSB
MSB +1 +2 +3 +4 +5
Figure 7. Right Justified Data
-7 -6 -5 -4 -3 -2 -1 LSB
18
DS566PP2