CDB5378 Datasheet, PDF (23/72 Pages) Cirrus Logic – Single-channel Seismic Evaluation System

CDB5378
If no system clock is supplied to CDB5378, the DIGITAL FILTER CLOCK jumper (J16) can select a PLL
input clock from a local oscillator. Using a clock divider, the on-board oscillator produces 1.024 MHz,
2.048 MHz, 4.096 MHz and 32.768 MHz clock outputs that can be applied to the CS5378 CLK input.
Specification
Oscillator - Citizen 32.768 MHz VCXO
Surface Mount Package Type
Supply Voltage, Current
Frequency Stability, Pullability
Startup Time
Value
CSX750VBEL32.768MTR
Leadless 6-Pin, 5x7 mm
3.3 V, 11 mA
± 50 ppm, ± 90 ppm
4 ms
Specification
Clock Divider - TI LittleLogic D-Flop
Surface Mount Package Type
Supply Voltage, Current
Value
SN74LVC2G74DCTR
SSOP8-199
3.3 V, 10 µA
2.3.2 Interface CPLD
A Xilinx CPLD is included on CDB5378 (XCR3128XL-10VQ100I) as an interface between the CS5378
digital filter and the microcontroller. By default the CPLD only passes through the interface signals, but
can be reprogrammed to disconnect the on-board 8051 microcontroller and connect to another external
microcontroller through the spare dual-row headers. Control signals taken off the CDB5378 board to an
external microcontroller should pair with a ground return wire to maintain signal integrity.
Free software tools and an inexpensive hardware programmer for the Xilinx CPLD are available from the
internet (http://www.xilinx.com). The hardware programmer interfaces with the Xilinx JTAG programming
port (J39) on CDB5378. Note that early versions of the Xilinx WebPack tools (7.1i SP1 and earlier) have
a bug in the JEDEC programming file for the CPLD included on CDB5378, and WebPack version 7.1i SP2
or later is required.
Included below is the default Verilog HDL file used by CDB5378 inside the interface CPLD. Comparing
the input and output definitions of this file with the CPLD schematic pinout should demonstrate how sig-
nals are selected and passed through from the microcontroller to the CS5378 digital filter. Several signal
connections to the CPLD are not defined in the default HDL file, but are routed to the CPLD on CDB5378
for convenience during custom reprogramming.
DS639DB3
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