CDB5378 Datasheet, PDF (21/72 Pages) Cirrus Logic – Single-channel Seismic Evaluation System

CDB5378
Configuration and data collection are through the SPI port.
SPI1 Signals
DRDYz
SCK
MISO
MOSI
SS:EECSz
Description
Data ready output, active low
Serial clock
Master in / slave out serial data
Master out / slave in serial data
Serial chip select, active low
Modulator ∆Σ data is input through the modulator interface, and test DAC ∆Σ data is generated by the test
bit stream generator.
Modulator Signals
MCLK
MSYNC
MDATA
MFLAG
TBSDATA
Description
Modulator clock output
Modulator synchronization output
Modulator delta-sigma data inputs
Modulator over-range flag inputs
Test DAC delta-sigma data output
Amplifier, modulator and test DAC pin settings are controlled through the GPIO port.
GPIO Signals
GPIO[0]:MUX[0]
GPIO[1..3]:MODE[0..2]
GPIO[4..6]:GAIN[0..2]
GPIO[7]:MUX[1]
Description
Amplifier input mux selection
Test DAC mode selection
Amplifier gain / test DAC attenuation
Amplifier input mux selection
2.3.1.1 Reset Options - BOOT, PLL
Immediately following the reset signal rising edge, the CS5378 digital filter latches the states of the
GPIO[4..6]:PLL[0..2] and GPIO7:BOOT pins. The reset states of the GPIO[4..6]:PLL[0..2] pins select the
master clock input frequency and type, while the reset state of the GPIO7:BOOT pin selects how the
CS5378 digital filter receives configuration data.
At reset the CS5378 digital filter GPIO pins default as inputs with weak pull-up resistors enabled. If left
floating, the GPIO state reads high at reset because of the internal pull-up resistor. A four-position DIP
switch on CDB5378 (S5) can connect 10k Ω pull-down resistors to the GPIO[4..6]:PLL[0..2] or
GPIO7:BOOT pins so they will read low at reset. Because the pin states are latched at reset, GPIO pins
can be programmed and used normally after reset without affecting the PLL and BOOT selections.
Detailed information about the PLL input clock and BOOT mode selections at reset can be found in the
CS5378 data sheet.
DS639DB3
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