EV-2 Datasheet, PDF (20/44 Pages) Cirrus Logic – Digital Audio Networking Processor

CobraNet™ EV-2
LED Control
There are two bit registers to control the state of each of three LEDs. The mapping of
control bits to LED behavior is described in Table 10 on page 20. The data bit is always
AD0. Note that blink overrides on/off but when blink is turned off the LED will go to the
state designated by the On/Off bit.
On/Off Blink Status
0
0
off
1
0
on
0
1
blink
1
1
blink
Table 10: LED Status
Calibrating the ADC
There is a ten-second warm-up time to allow both the ADC and DAC to settle. All audio is
muted during this 10-second warm-up. This warm-up cycle only takes place on system
reset which is initiated by either power-up or a user pushing the reset button (SW508).
Version Control
The FPGA contains three hardwired eight-bit registers that contain an ASCII version
number of the FPGA configuration file. The microcontroller reads these registers for
version control and reporting purposes.
Mute Control
Muting comes from three different sources 1) the microcontroller can mute or unmute
audio by writing to a bit control register. There is one mute bit control register for each
output audio path, 2) the CM asserts its mute signal, and 3) all audio is unconditionally
muted during a power on/reset warm-up cycle.
Rev. 2.1
20