EV-2 Datasheet, PDF (16/44 Pages) Cirrus Logic – Digital Audio Networking Processor

CobraNet™ EV-2
Memory
Location
R/W
Description
0x8000
0x8001
W Bit register for green LED, CR903. 0=LED on, 1=LED off.
Refer to Table 10 on page 20 for this and other LED regis-
ters.
W Bit register for red LED, CR904. 0=LED on, 1=LED off.
0x8002
0x8004
0x8005
0x8006
0x8008
0x8009
0x800A
0x800B
0x8010
0x8010
0x8011
0x8012
0x8018
W Bit register for yellow LED, CR905. 0=LED on, 1=LED off.
W Bit register for green LED blink control. 0=blink off, 1=blink
on.
W Bit register for green LED blink control. 0=blink off, 1=blink
on.
W Bit register for green LED blink control. 0=blink off, 1=blink
on.
W DAC audio routing address (see Table 7 on page 18).
W Bit register for DAC mute signal. 0=mute on, 1=mute off.
W Bit register for sample rate mode. 0=48k, 1=96k. Note: use
AD1 instead of AD0
W Bit register for DAC reset signal. 0=reset on, 1=reset off.
R Audio Calibration Status. 1=Calibrating, 0=Ready. See the
Calibrating Audio section for details.
W Manual ADC Calibration. 0=Normal, 1=Calibrate. See the
Calibrating the ADC section for details. (Rev. D applicable
only)
W Bit register for ADC slave/master control. 0=Slave, 1=Mas-
ter. (Rev. D applicable only)
W ADC high pass filter (HPF) select. 0=Enabled, 1=Disabled.
W AES3 audio routing address (see Table 7 on page 18).
0x8019
0x8020
W Bit register for AES3 mute signal. 0=AES output muted,
1=Unmuted.
W SSI 0 audio routing address (see Table 7 on page 18).
0x8021
W Bit register for SSI 0 mute signal. 0=Muted, 1=Unmuted.
0x8028
W SSI 1 audio routing address (see Table 7 on page 18).
0x8029
W Bit register for SSI 1 mute signal. 0=Muted, 1=Unmuted.
Table 6: Microcontroller Memory Map of Upper 32k After FPGA Configuration
Rev. 2.1
16