EV-2 Datasheet, PDF (13/44 Pages) Cirrus Logic – Digital Audio Networking Processor

CobraNet™ EV-2
Port 3: See Table 5 on page 13.
Bit #
Name of Signal
I/O
Description
0 RXD
1 TXD
I RS232 serial port receive signal.
O RS232 serial port transmit signal
2 HREQ#
O Connected to the CM module host
request signal. See CobraNet
Technical Datasheet for a com-
plete description of this signal.
3 HACK#
I Connected to the CM module host
acknowledge signal. See Cobra-
Net Technical Datasheet for a
complete description of this signal.
May be used as an interrupt
request on the microcontroller.
4 Watchdog
5 MCU_P35
6 WR#
I Watchdog signal from the CM
I/O Connected to SCI_CLK via the
FPGA. Also used to detect sample
rate.
O Microcontroller write signal.
7 RD#
O Microcontroller read signal.
Table 5: Port 3 Signal Descriptions
Interfacing the Microcontroller to the CM
Please refer to the EV-2 schematic, found in Appendix D for information regarding interfacing
to the CM.
The CM has a host interface that allows a host processor (such as an 8051 microcontroller)
to interface to the DSP on the CM. From a hardware perspective the interface to the CM-1
and CM-2 is almost the same,. The host interface signals are a data strobe signal, HDS#; a
read/write line, HRW, an 8-bit bi-directional data bus, HD0-HD7, and three address lines,
HA0-HA2 on the CM-1 and four address lines, HA0-HA3 on the CM-2. The HEN# line has
been configured by the CobraNet software to be ignored or seen as a logic low. Given this
host configuration, the interface of the microcontroller to the CM host port is straightforward.
In addition to the above signals there are two more, HACK# and HREQ# which can be used
as flags to indicate a state change on the CM.
With regard to the CM-1 which uses a Motorola DSP56303, care must be taken with the
timing of HDS# and HWR. Motorola's timing specifications for the DSP56303 host port in a
non-multiplexed, single data strobe mode requires a set up time from the falling edge of
HWR# to the falling edge of HDS# of 4.7ns and the hold time from the rising edge of HDS# to
the rising edge of HWR# of 3.3ns. The pulse of the HDS# signal must be wholly within the
pulse of the HWR# signal with the constraints stated above. Please refer to Motorola's
DSP56303 Technical Data sheet for complete information regarding timing and interface
issues. This is available for download from the Motorola web site at
http://www.freescale.com.
13
Rev. 2.1