EV-2 Datasheet, PDF (17/44 Pages) Cirrus Logic – Digital Audio Networking Processor

CobraNet™ EV-2
Memory
Location
R/W
Description
0x8030
0x8031
0x8038
W SSI 2 audio routing address (Table 7 on page 18).
W Bit register for SSI 2 mute signal. 0=Muted, 1=Unmuted.
W SSI 3 audio routing address (Table 7 on page 18).
0x8039
0x8040
0x8041
0x8042
W Bit register for SSI 3 mute signal. 0=Muted, 1=Unmuted.
Note 1 CM-1 Host Port ICR register. CM-2 Message-A register.
Note 1 CM-1 Host Port CVR register. CM-2 Message-B register.
Note 1 CM-1 Host Port ISR register. CM-2 Message-C register.
0x8043
0x8044
0x8045
0x8046
Note 1 CM-1 Host Port IVR register. CM-2 Message-D register.
Note 1 CM-1: Unused. CM-2 Data-A register.
Note 1 CM-1 Host Port Data register high. CM-2 Data-B register.
Note 1 CM-1 Host Port Data register middle. CM-2 Data-C register.
0x8047
0x8048
0x8049
0x8051
0x8052
Note 1 CM-1 Host Port Data register low. CM-2 Data-D register.
Note 1 CM-2 Host Control Register.
Note1 CM-2 Host Status Register.
W Bit register for Host reset signal. 0=Asserted, 1=Deas-
serted.
W Bit register for Host interface mode. 0=Motorola, 1=Intel
0x8054
0x8058
W Signal MCU_P35 is either SCI_CLK from the CM or FS1
from the CM. 0=SCI_CLK, 1=FS1.
R/W Auxiliary lines. Not used, for test purposes only.
0x8060
0x8061
0x8062
0x8070
R FPGA configuration major version.
R FPGA configuration minor version.
R FPGA configuration revision number.
R/W Sinewave Gain register. See Table 9 on page 19.
0x8078 R/W Sinewave Frequency register. See Table 8 on page 19.
Table 6: Microcontroller Memory Map of Upper 32k After FPGA Configuration
Note 1: The FPGA only decodes this address. The actual register is located on the CM. See the
Motorola DSP56303 users manual or the CS18101 manual for a discussion of each of these host
port registers.
17
Rev. 2.1