EV-2 Datasheet, PDF (15/44 Pages) Cirrus Logic – Digital Audio Networking Processor

CobraNet™ EV-2
Interfacing Serial Audio to the CM
In general, interfacing to most off-the-shelf A/D and D/A converters is straightforward and the CM
is no exception. Most signals for a direct connection to these as well as other audio ICs such as
the CS8420 AES3 transceiver, are available on the CM module interface connector. Most
converters provide for a choice of bit clock and sample (frame) clock polarity, as well as audio
data formats such as SPI™ or I2S.
The A/D converter, a Cirrus Logic CS5381 is configured for slave operation, which means that it
requires a bit clock and a sample (frame) clock input. The master, bit and sample clocks are
direct connections from FS512, SCK and FS1 respectively, as is the data stream which comes
from one of the SSI ports. The CM can be configured to clock data from either edge of the bit
clock, as well as allowing for specifying the polarity of the sample clock. (See the CobraNet
website and the CobraNet Technology Datasheet for more information.) This is important since
the CS5396 works with sample pairs which need to be phase aligned. The polarity of the sample
clock specifies this alignment. For the EV-2 application, the SSI ports of the CM have been
programmed to send two channels per port. This allows a straightforward connection without any
demultiplexing.
The connection to the Cirrus Logic CS4398 D/A converter is similarly straightforward. Like the
SCS5381, it uses the FS512, bit clock and sample clock directly from the CM. Data to the DAC
and from the ADC are also direct except that they pass through a selector circuit in the FPGA. If
a particular design does not include multiple sources of audio, then the connection can be direct
to the CM interface connector.
FPGA
The Field Programmable Logic Array is a Xilinx Spartan(tm) XCS10XLVQ100-4. It is mapped into
the microcontroller's memory space. The microcontroller must configure the FPGA after power
on or reset. Express mode configuration is used for this part. Refer to the Xilinx Spartan(tm) XL
family data sheet for more information on the Express mode configuration operation. This data
sheet can be found at the Xilinx web site, http://www.xilinx.com/. The address for configuration is
0x8800. Once configured, the FPGA's two main functions are to decode the microcontroller's
address signals and to route audio from a user selected source to a user selected destination.
Secondary functions are to generate a sine wave signal and implement registers whose function
are mostly of a control nature. A discussion of the memory decoding, routing, sine wave
generation and other functions follow.
The memory map of the upper 32k of the microcontroller space after configuration, is shown in
Table 6 on page 16. Most bit-defined locations use the least significant microcontroller data bus
signal AD0 as the controlling bit. Other data bits are ignored on these registers. Power on and
reset default for all registers is 0 unless specified otherwise.
15
Rev. 2.1