CS2200-CP Datasheet, PDF (20/26 Pages) Cirrus Logic – Fractional-N Frequency Synthesizer

8.2.3
PLL Clock Output Disable (ClkOutDis)
This bit controls the output driver for the CLK_OUT pin.
ClkOutDis
0
1
Application:
Output Driver State
CLK_OUT output driver enabled.
CLK_OUT output driver set to high-impedance.
“PLL Clock Output” on page 14
CS2200-CP
8.3 Device Configuration 1 (Address 03h)
7
RModSel2
6
RModSel1
5
RModSel0
4
Reserved
3
Reserved
2
1
0
AuxOutSrc1 AuxOutSrc0 EnDevCfg1
8.3.1
R-Mod Selection (RModSel[2:0])
Selects the R-Mod value, which is used as a factor in determining the PLL’s Fractional N.
RModSel[2:0]
000
001
010
011
100
101
110
111
Application:
R-Mod Selection
Left-shift R-value by 0 (x 1).
Left-shift R-value by 1 (x 2).
Left-shift R-value by 2 (x 4).
Left-shift R-value by 3 (x 8).
Right-shift R-value by 1 (÷ 2).
Right-shift R-value by 2 (÷ 4).
Right-shift R-value by 3 (÷ 8).
Right-shift R-value by 4 (÷ 16).
“Manual Ratio Modifier (R-Mod)” on page 12
8.3.2
Auxiliary Output Source Selection (AuxOutSrc[1:0])
Selects the source of the AUX_OUT signal.
AuxOutSrc[1:0]
00
01
10
11
Application:
Auxiliary Output Source
RefClk.
Reserved.
CLK_OUT.
PLL Lock Status Indicator.
“Auxiliary Output” on page 14
Note: When set to 11, AuxLckCfg sets the polarity and driver type (“AUX PLL Lock Output Configura-
tion (AuxLockCfg)” on page 22).
8.3.3
Enable Device Configuration Registers 1 (EnDevCfg1)
This bit, in conjunction with EnDevCfg2, enables control port mode. Both bits must be set to 1 during ini-
tialization.
EnDevCfg1
0
1
Application:
Register State
Disabled.
Enabled.
“SPI / I²C Control Port” on page 16
Note: EnDevCfg2 must also be set to enable control port mode (“SPI / I²C Control Port” on page 16).
20
DS759PP1