CS2200-CP Datasheet, PDF (15/26 Pages) Cirrus Logic – Fractional-N Frequency Synthesizer

5.5 Clock Output Stability Considerations
CS2200-CP
5.5.1
Output Switching
CS2200 is designed such that re-configuration of the clock routing functions do not result in a partial clock
period on any of the active outputs (CLK_OUT and/or AUX_OUT). In particular, enabling or disabling an
output, changing the auxiliary output source between REF_CLK and CLK_OUT, and the automatic dis-
abling of the output(s) during unlock will not cause a runt or partial clock period.
The following exceptions/limitations exist:
• Enabling/disabling AUX_OUT when AuxOutSrc = 11 (unlock indicator).
• Switching AuxOutSrc[1:0] to or from 11 (unlock indicator)
(Transitions between AuxOutSrc[1:0] = [00,10] will not produce a glitch).
• Changing the ClkOutUnl bit while the PLL is in operation.
When any of these exceptions occur, a partial clock period on the output may result.
5.5.2
PLL Unlock Conditions
Certain changes to the clock inputs and registers can cause the PLL to lose lock which will affect the pres-
ence the clock signal on CLK_OUT. The following outlines which conditions cause the PLL to go un-
locked:
• Changes made to the registers which affect the Fraction-N value that is used by the Frequency Syn-
thesizer. This includes all the bits shown in Figure 7 on page 13.
• Any discontinuities on the Timing Reference Clock, REF_CLK.
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