CS4215 Datasheet, PDF (17/52 Pages) Cirrus Logic – 16-Bit Multimedia Audio Codec

Wait at least 12 SCLK
periods for FSYNC and
SCLK to three-state
Set external controller to
receive SCLK and FSYNC
from the codec
DS76F2
Lower output level to
maximum attenuation
Mute the speaker output
Set D/C low
CS4215
Y
Codec programmed for
Master mode & ITS=0?
N
Set external controller to
drive SCLK and FSYNC
into the codec
1 _{This is a software design choice,}
not a run-time conditional branch.
Poll for CLB=0? ¹
N
Y
Send valid control information
with CLB=0
Read back and verify control information.
Mask off reserved bits
N
CLB=0?
Y
Set CLB=1 and send at least
two more frames of valid
control information ²
Is codec
Y
programmed for
Master mode?
N
Set D/C high.
Transmit/receive data with attenuated outputs
and muted speaker for 194 FSYNC cycles
while codec executes offset calibration
Transmit/receive audio data
with desired level settings
n=5
Send valid control information
with CLB=0
n=n-1
n = 0?
N
Y
2 _{This will cause the codec to}
ignore any further bus activity.
The SDOUT pin will be held in
the high impedance state after
transmitting 1 frame with CLB=1
Figure 11. Control Mode Flow Chart
17