CS4215 Datasheet, PDF (15/52 Pages) Cirrus Logic – 16-Bit Multimedia Audio Codec

CS4215
ways 256 times the sample frequency and scales
with the selected sample frequency on the mas-
ter, the slave devices will automatically scale
with changes in the master codec’s sample fre-
quency.
CS4215s are time division multiplexed onto the
bus using the Time Slot Out (TSOUT) and Time
Slot In (TSIN) signals. TSOUT is an output sig-
nal that is high for one SCLK bit time, and
indicates that the CS4215 is about to release the
bus. TSIN is an input signal that informs the
CS4215 that the next time slot is available for it
to use. The first device in the chain uses FSYNC
as its TSIN signal. All subsequent devices use
the TSOUT of the previous device as its TSIN
input. TSIN must be high for at least 1 SCLK
period and fall at least 2 SCLKs before start of a
new frame.
Serial Interface Operation
The serial interface format has a variable number
of time slots, depending on the number of
CS4215s attached to the bus. All time slots have
8 bits. Each CS4215 requires 8 time slots (64
bits) to communicate all data (see Figure 9).
CONTROL MODE
The Control Mode is used to set up the CS4215
for subsequent operation in Data Mode by load-
ing the internal control registers. Control mode is
asserted by bringing D/C low. If D/C is low dur-
ing power up, then the CS4215 will enter control
mode immediately. The SCLK and FSYNC pins
are tri-stated, and the CS4215 will receive SCLK
and FSYNC from an external source. If the
CS4215 is in master mode (SCLK and FSYNC
are outputs) and D/C is brought low, then SCLK
& FSYNC will continue to be driven for a mini-
mum of 4 and a maximum of 12 SCLKs, if the
ITS bit = 0. If ITS is 1, SCLK and FSYNC will
three-state immediately after D/C goes low. If
D/C is brought low when the codec is pro-
grammed as master with ITS=0, the codec will
DS76F2
timeout and release FSYNC and SCLK within
100µs. The values in the control registers for
control of the serial ports are ignored in control
mode. The data received on SDIN is stored into
the control registers which have addresses
matching their time slots. The data in the regis-
ters is transmitted on SDOUT with the time slot
equal to the register number (see Figure 10).
The steps involved when going from data mode
to control mode and back are shown in the flow
chart in Figure 11.
Control Formats
The CS4215 control registers have the functions
and time slot assignments shown in Table 1. The
register address is the time slot number when
D/C is 0. Reserved bits should be written as 0
and could be read back as 0 or 1. When compar-
ing data read back, reserved bits should be
masked. The SDOUT pin goes into a
high-impedance state prior to Time Slot 1 and
after Time Slot 8. The data listed below the reg-
ister is its reset state.
The parallel port register is used to read and
write the two open-drain input/output pins. The
outputs are all set to 1 on RESET. PIO bits are
read only in control mode. Note that, since PIO
signals are open drain signals, an external device
Time slot
1
2
3
4
5
6
7
8
Description
Status
Data Format
Serial Port Control
Test
Parallel Port
RESERVED
Revision
RESERVED
Table 1. Control Registers
15