CS2300-OTP Datasheet, PDF (16/28 Pages) Cirrus Logic – Fractional-N Clock Multiplier with Internal LCO

CS2300-OTP
ratio R_EFF, the final calculation used to determine the output to input clock ratio. The conceptual diagram
in Figure 10 summarizes the features involved in the calculation of the ratio values used to generate the
fractional-N value which controls the Frequency Synthesizer. The subscript ‘4’ indicates the modal param-
eters.
Effective Ratio REFF
M[1:0] pins
User Defined Ratio RUD
Ratio 0
Ratio 1
Ratio 2
Ratio Format
12.20
20.12
Ratio 3
LFRatioCfg
M2 pin
RModSel[1:0]4
Ratio
Modifier
Auto
R-Mod
LCO
Digital PLL &
Fractional N Logic
Dynamic Ratio, ‘N’
AutoRMod4
or M2 pin
FsDet[1:0]
Frequency Reference Clock
(CLK_IN)
Frequency
Synthesizer
PLL Output
Figure 10. Ratio Feature Summary
Referenced Control
Parameter Definition
Ratio 0-3................................“Ratio 0 - 3” on page 21
M[1:0] pins.............................“M1 and M0 Mode Pin Functionality” on page 17
LFRatioCfg ............................“Low-Frequency Ratio Configuration (LFRatioCfg)” on page 22
RModSel[1:0] ........................“R-Mod Selection (RModSel[1:0])” section on page 20
AutoRMod .............................“Auto R-Modifier Enable (AutoRMod)” on page 21
5.5 PLL Clock Output
The PLL clock output pin (CLK_OUT) provides a buffered version of the output of the frequency synthesizer.
The driver can be set to high-impedance with the M2 pin when the M2Config[1:0] global parameter is set to
either 000 or 010. The output from the PLL automatically drives a static low condition while the PLL is un-
locked (when the clock may be unreliable). This feature can be disabled by setting the ClkOutUnl global
parameter, however the state CLK_OUT may then be unreliable during an unlock condition.
ClkOutUnl
PLL Locked/Unlocked
0
0
2:1 Mux
1
0
2:1 Mux
M2 pin with
M2Config[1:0] = 000, 010
PLL Clock Output
PLLClkOut
PLL Clock Output Pin
(CLK_OUT)
PLL Output
1
Figure 11. PLL Clock Output Options
Referenced Control
Parameter Definition
ClkOutUnl..............................“Enable PLL Clock Output on Unlock (ClkOutUnl)” on page 22
ClkOutDis ..............................“M2 Configured as Output Disable” on page 18
M2Config[2:0]........................“M2 Pin Configuration (M2Config[2:0])” on page 22
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DS844PP1