CS2300-OTP Datasheet, PDF (11/28 Pages) Cirrus Logic – Fractional-N Clock Multiplier with Internal LCO

CS2300-OTP
Regardless of the setting of the ClkSkipEn parameter the PLL output will continue for 2²³ LCO cycles
(518 ms to 634 ms) after CLK_IN is removed (see Figure 5). This is true as long as CLK_IN does not glitch
or have an effective change in period as the clock source is removed, otherwise the PLL will interpret this
as a change in frequency causing clock skipping and the 2²³ LCO cycle time-out to be bypassed and the
PLL to immediately unlock. If the prior conditions are met while CLK_IN is removed and 2²³ LCO cycles
pass, the PLL will unlock and the PLL_OUT state will be determined by the ClkOutUnl parameter; See
“PLL Clock Output” on page 16. If CLK_IN is re-applied after such time, the PLL will remain unlocked for
the specified time listed in the “AC Electrical Characteristics” on page 7 after which lock will be acquired
and the PLL output will resume.
2²³ LCO cycles
2²³ LCO cycles
Lock Time
Lock Time
CLK_IN
CLK_IN
ClkSkipEn=0 or 1
ClkOutUnl=0
PLL_OUT
ClkSkipEn=0 or 1
ClkOutUnl=1
PLL_OUT
UNLOCK
UNLOCK
Figure 5. CLK_IN removed for > 2²³ LCO cycles
= invalid clocks
f CLK_IN is removed and then reapplied within 2²³ LCO cycles but later than t_CS, the ClkSkipEn param-
eter will have no effect and the PLL output will continue until CLK_IN is re-applied (see Figure 6). Once
CLK_IN is re-applied, the PLL will go unlocked only for the time it takes to acquire lock; the PLL_OUT
state will be determined by the ClkOutUnl parameter during this time.
2²³ LCO cycles
tCS
2²³ LCO cycles
tCS
Lock Time
Lock Time
CLK_IN
CLK_IN
ClkSkipEn=0 or 1
ClkOutUnl=0
PLL_OUT
ClkSkipEn=0 or 1
ClkOutUnl=1
PLL_OUT
UNLOCK
UNLOCK
= invalid clocks
Figure 6. CLK_IN removed for < 2²³ LCO cycles but > t_CS
If CLK_IN is removed and then re-applied within t_CS, the ClkSkipEn parameter determines whether
PLL_OUT continues while the PLL re-acquires lock (see Figure 7). When ClkSkipEn is disabled and
CLK_IN is removed the PLL output will continue until CLK_IN is re-applied at which point the PLL will go
unlocked only for the time it takes to acquire lock; the PLL_OUT state will be determined by the ClkOutUnl
parameter during this time. When ClkSkipEn is enabled and CLK_IN is removed the PLL output clock will
DS844PP1
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