CAT28C65B_05 Datasheet, PDF (9/13 Pages) Catalyst Semiconductor – 64K-Bit CMOS PARALLEL EEPROM

CAT28C65B
(which can be loaded in any order) during the first and
subsequent write cycles. Each successive byte load
cycle must begin within t_{BLC MAX} of the rising edge of the
preceding WE pulse. There is no page write window
limitation as long as WE is pulsed low within t_{BLC MAX}.
Upon completion of the page write sequence, WE must
stay high a minimum of tBLC MAX for the internal automatic
program cycle to commence. This programming cycle
consists of an erase cycle, which erases any data that
existed in each addressed cell, and a write cycle, which
writes new data back into the cell. A page write will only
write data to the locations that were addressed and will
not rewrite the entire page.
DATA Polling
DATA polling is provided to indicate the completion of
write cycle. Once a byte write or page write cycle is
initiated, attempting to read the last byte written will
output the complement of that data on I/O7 (I/O0–I/O6
Figure 7. DATA Polling
ADDRESS
are indeterminate) until the programming cycle is
complete. Upon completion of the self-timed write cycle,
all I/O’s will output true data during a read cycle.
Toggle Bit
In addition to the DATA Polling feature, the device offers
an additional method for determining the completion of
a write cycle. While a write cycle is in progress, reading
data from the device will result in I/O₆ toggling between
one and zero. However, once the write is complete, I/O₆
stops toggling and valid data can be read from the
device.
Ready/BUSY (RDY/BUSY)
The RDY/BUSY pin is an open drain output which
indicates device status during programming. It is pulled
low during the write cycle and released at the end of
programming. Several devices may be OR-tied to the
same RDY/BUSY line.
CE
WE
OE
I/O7
Figure 8. Toggle Bit
WE
tOEH
DIN = X
tOE
tWC
DOUT = X
tOES
DOUT = X
CE
tOEH
tOE
OE
tOES
I/O6
(1)
(1)
tWC
9
Doc. No. 1009, Rev. E