CAT28C65B_05 Datasheet, PDF (8/13 Pages) Catalyst Semiconductor – 64K-Bit CMOS PARALLEL EEPROM

CAT28C65B
falling edge of WE or CE, whichever occurs last. Data,
conversely, is latched on the rising edge of WE or CE,
whichever occurs first. Once initiated, a byte write cycle
automatically erases the addressed byte and the new
data is written within 5 ms.
Page Write
The page write mode of the CAT28C65B (essentially an
extended BYTE WRITE mode) allows from 1 to 32 bytes
of data to be programmed within a single EEPROM write
cycle. This effectively reduces the byte-write time by a
factor of 32.
Following an initial WRITE operation (WE pulsed low, for
tWP, and then high) the page write mode can begin by
issuing sequential WE pulses, which load the address
and data bytes into a 32 byte temporary buffer. The page
address where data is to be written, specified by bits A5
to A12, is latched on the last falling edge of WE. Each
byte within the page is defined by address bits A0 to A4
Figure 5. Byte Write Cycle [CE Controlled]
tWC
ADDRESS
tAS
CE
tAH
tCW
tBLC
tOEH
OE
tOES
tCS
tCH
WE
tRB
RDY/BUSY
HIGH-Z
DATA OUT
HIGH-Z
HIGH-Z
DATA IN
DATA VALID
tDS
tDH
Figure 6. Page Mode Write Cycle
OE
CE
tWP
tBLC
WE
ADDRESS
I/O
Doc. No. 1009, Rev. E
BYTE 0 BYTE 1
BYTE 2
BYTE n BYTE n+1
tWC
LAST BYTE
BYTE n+2
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