CAT25C01_05 Datasheet, PDF (9/15 Pages) Catalyst Semiconductor – 1K/2K/4K SPI Serial CMOS EEPROM

CAT25C01, CAT25C02, CAT25C04
DESIGN CONSIDERATIONS
ming is continued. On power up, SO is in a high
The CAT25C01/02/04 powers up in a write disable state
and in a low power standby mode. A WREN instruction
must be issued to perform any writes to the device after
power up. Also,on power up CS should be brought low
impedance. If an invalid op code is received, no data will
be shifted into the CAT25C01/02/04, and the serial
output pin (SO) will remain in a high impedance state
until the falling edge of CS is detected again.
to enter a ready state and receive an instruction. After
When powering down, the supply should be taken down
a successful byte/page write or status register write, the
to 0V, so that the CAT25C01/02/04 will be reset when
CAT25C01/02/04 goes into a write disable mode. CS
power is ramped back up. If this is not possible, then,
must be set high after the proper number of clock cycles
following a brown-out episode, the CAT25C01/02/04
to start an internal write cycle. Access to the array
during an internal write cycle is ignored and program-
can be reset by refreshing the contents of the Status
Register (See Application Note AN10).
ts ^{Figure 8. Page Write Instruction Timing}
r ^CS
a ^{0 1 2 3 4 5 6 7 8}
13 14 15 16-23 24-31 16+(N-1)x8-1..16+(N-1)x8 16+Nx8-1
SK
P OPCODE
BYTE ADDRESS
DATA IN
SI
0 0 0 0 X0* 0 1 0 A7
Data Data Data
A0 _{Byte 1 Byte 2 Byte 3}
Data Byte N
7..1
0
HIGH IMPEDANCE
d _SO
Note: Dashed Line= mode (1, 1) – – – – – *X=0 for CAT25C01, CAT25C02; X=A8 for CAT25C04
e _{Figure 9. HOLD Timing}
u _CS
tin ^SCK
HOLD
on ^SO
tCD
tHD
tHZ
Note: Dashed Line= mode (1, 1) – – – – –
tCD
tHD
HIGH IMPEDANCE
tLZ
isc ^{Figure 10. WP Timing}
t _WPS
t _WPH
D ^CS
SCK
WP
WP
Note: Dashed Line= mode (1, 1) – – – – –
© 2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
9
Doc. No. 1105, Rev. B