CAT25C01_05 Datasheet, PDF (6/15 Pages) Catalyst Semiconductor – 1K/2K/4K SPI Serial CMOS EEPROM

CAT25C01, CAT25C02, CAT25C04
STATUS REGISTER
to the status register, (including the block protect bits
and the WPEN bit) and the block protected sections in
The Status Register indicates the status of the device. the memory array when the chip is hardware write
The RDY (Ready) bit indicates whether the CAT25C01/ protected. Only the sections of the memory array that
02/04 is busy with a write operation. When set to 1 a are not block protected can be written. Hardware write
write cycle is in progress and when set to 0 the device protection is disabled when either WP pin is high or the
indicates it is ready. This bit is read only. The WEL (Write WPEN bit is zero.
Enable) bit indicates the status of the write enable latch.
When set to 1, the device is in a Write Enable state and
when set to 0 the device is in a Write Disable state. The
DEVICE OPERATION
WEL bit can only be set by the WREN instruction and can
be reset by the WRDI instruction.
The BP0 and BP1 (Block Protect) bits indicate which
ts ^{blocks are currently protected. These bits are set by the}
user issuing the WRSR instruction. The user is allowed
to protect quarter of the memory, half of the memory or
r _{the entire memory by setting these bits. Once protected,}
the user may only read from the protected portion of the
a _{array. These bits are non-volatile.}
The WPEN (Write Protect Enable) is an enable bit for the
P _{WP pin. The WP pin and WPEN bit in the status register}
control the programmable hardware write protect fea-
ture. Hardware write protection is enabled when WP is
d low and WPEN bit is set to high. The user cannot write
e _{Figure 2. WREN Instruction Timing}
u ^CS
Write Enable and Disable
The CAT25C01/02/04 contains a write enable latch.
This latch must be set before any write operation. The
device powers up in a write disable state when V_CC is
applied. WREN instruction will enable writes (set the
latch) to the device. WRDI instruction will disable writes
(reset the latch) to the device. Disabling writes will
protect the device against inadvertent writes.
READ Sequence
The part is selected by pulling CS low. The 8-bit read
instruction is transmitted to the CAT25C01/02/04,
followed by the 8-bit address for CAT25C01/02/04 (for
the CAT25C04, bit 3 of the read data instruction contains
address A8).
tin ^SCK
SI
0 0 0 0 0 1 10
on SO
Note: Dashed Line = mode (1, 1)
c _{Figure 3. WRDI Instruction Timing}
Dis ^CS
HIGH IMPEDANCE
SCK
SI
SO
Note: Dashed Line = mode (1, 1)
Doc. No. 1105, Rev. B
0 0 0 0 0 1 00
HIGH IMPEDANCE
6
© 2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice