CAT25C01_05 Datasheet, PDF (3/15 Pages) Catalyst Semiconductor – 1K/2K/4K SPI Serial CMOS EEPROM

CAT25C01, CAT25C02, CAT25C04
A.C. CHARACTERISTICS
SYMBOL PARAMETER
CAT25CXX-1.8
CAT25CXX
1.8V-5.5V 2.5V-5.5V
4.5V-5.5V
Min. Max. Min. Max. Min. Max.
Test
UNITS Conditions
t_SU
Data Setup Time
50
20
20
ns
t_H
Data Hold Time
50
20
20
ns
t_WH
SCK High Time
250
75
40
t_WL
SCK Low Time
250
75
40
f_SCK
Clock Frequency
DC
1 DC
5 DC
t_LZ
HOLD to Output Low Z
50
50
t_RI(1)
Input Rise Time
2
2
t_FI(1)
Input Fall Time
2
2
t_HD
HOLD Setup Time
100
40
40
t_CD
t_WC(4)
t_V
d _tHO
t_DIS
e _tHZ
u _tCS
t_CSS
tin ^tCSH
t_WPS
t_WPH
HOLD Hold Time
100
Write Cycle Time
Output Valid from Clock Low
Output Hold Time
0
Output Disable Time
HOLD to Output High Z
CS High Time
500
CS Setup Time
500
CS Hold Time
500
WP Setup Time
150
WP Hold Time
150
40
5
250
0
250
150
100
100
100
50
50
40
5
75
0
75
50
100
100
100
50
50
n _{Power-Up Timing(1)(3)}
o _Symbol
c ^tPUR
tPUW
Parameter
Power-up to Read Operation
Power-up to Write Operation
Max.
1
1
is ^NOTE:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
(2) AC Test Conditions:
D^{Input Pulse Voltages: 0.3VCC to 0.7VCC}
Input rise and fall times: ≤10ns
ns
ns
10 MHz
ts ⁵⁰
ns
2
µs
r ₂
µs
a_ns
P^ns
5
ms
C_L = 50pF
40
ns
(note 2)
ns
75
ns
50
ns
ns
ns
ns
ns
ns
Units
ms
ms
Input and output reference voltages: 0.5V_CC
Output load: current source I_OL max/I_OH max; C_L=50pF
(3) t_PUR and t_PUW are the delays required from the time V_CC is stable until the specified operation can be initiated.
(4) t_WC is the time from the rising edge of CS after a valid write sequence to the end of the internal write cycle.
© 2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
3
Doc. No. 1105, Rev. B