CAT25C01_05 Datasheet, PDF (8/15 Pages) Catalyst Semiconductor – 1K/2K/4K SPI Serial CMOS EEPROM

CAT25C01, CAT25C02, CAT25C04
During an internal write cycle, all commands will be address will remain constant. The only restriction is that
ignored except the RDSR (Read Status Register) the X (X=16 for CAT25C01/02/04) bytes must reside on
instruction.
the same page. If the address counter reaches the end
The Status Register can be read to determine if the write
cycle is still in progress. If Bit 0 of the Status Register is
set at 1, write cycle is in progress. If Bit 0 is set at 0, the
device is ready for the next instruction.
of the page and clock continues, the counter will “roll
over” to the first address of the page and overwrite any
data that may have been written. The CAT25C01/02/04
is automatically returned to the write disable state at the
completion of the write cycle. Figure 8 illustrates the
Page Write
page write sequence.
The CAT25C01/02/04 features page write capability.
After the initial byte, the host may continue to write up to
16 bytes of data to the CAT25C01/02/04. After each
byte of data received, lower order address bits are
ts ^{internally incremented by one; the high order bits of}
To write to the status register, the WRSR instruction
should be sent. Only Bit 2, Bit 3 and Bit 7 of the status
register can be written using the WRSR instruction.
Figure 7 illustrates the sequence of writing to status
register.
ar ^{Figure 6. Write Instruction Timing}
P ^CS
012345678
13 14 15 16 17 18 19 20 21 22 23
d _SK
e _OPCODE
BYTE ADDRESS
DATA IN
SI
0 0 0 0 0X* 0 1 0 A7
A0 D7 D6 D5 D4 D3 D2 D1 D0
tinu ^SO
HIGH IMPEDANCE
Note: Dashed Line= mode (1, 1) – – – – –
*X=0 for 25010, 25020 ; X=A8 for 25040
on ^{Figure 7. WRSR Timing}
c _CS
Dis ^SCK
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
OPCODE
DATA IN
SI
0
0
0
0
00
0
1
7
6
5
4
3
2
10
MSB
SO
HIGH IMPEDANCE
Note: Dashed Line= mode (1, 1) – – – – –
Doc. No. 1105, Rev. B
8
© 2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice