CAT25C128_05 Datasheet, PDF(7/12 Page) Catalyst Semiconductor

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CAT25C128_05 Datasheet, PDF (7/12 Pages) Catalyst Semiconductor – 128K/256K-Bit SPI Serial CMOS EEPROM

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CAT25C128/256

The WPEN (Write Protect Enable) is an enable bit for the

WP pin. The WP pin and WPEN bit in the status register

control the programmable hardware write protect fea-

ture. Hardware write protection is enabled when WP is

low and WPEN bit is set to high. The user cannot write

to the status register (including the block protect bits and

the WPEN bit) and the block protected sections in the

memory array when the chip is hardware write pro-

tected. Only the sections of the memory array that are

not block protected can be written. Hardware write

protection is disabled when either WP pin is high or the

WPEN bit is zero.

DEVICE OPERATION

Write Enable and Disable

The CAT25C128/256 contains a write enable latch. This

latch must be set before any write operation. The device

powers up in a write disable state when Vcc is applied.

WREN instruction will enable writes (set the latch) to the

device. WRDI instruction will disable writes (reset the

Figure 2. WREN Instruction Timing

latch) to the device. Disabling writes will protect the

device against inadvertent writes.

READ Sequence

The part is selected by pulling CS low. The 8-bit read

instruction is transmitted to the CAT25C128/256, followed

by the 16-bit address(the three Most Significant Bit is

donât care for 25C256 and four most significant bits are

don't care for 25C128).

After the correct read instruction and address are sent,

the data stored in the memory at the selected address is

shifted out on the SO pin. The data stored in the memory

at the next address can be read sequentially by continuing

to provide clock pulses. The internal address pointer is

automatically incremented to the next higher address

after each byte of data is shifted out. When the highest

address (7FFFh for 25C256 and 3FFFh for 25C128) is

reached, the address counter rolls over to 0000h allowing

the read cycle to be continued indefinitely. The

readoperation is terminated by pulling the CS high.

0 0 0 0 0 1 10

HIGH IMPEDANCE

Figure 3. WRDI Instruction Timing

0 0 0 0 0 1 00

Note: Dashed Line= mode (1, 1) â â â â

HIGH IMPEDANCE

Document No. 1018, Rev. I

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