CAT25C128_05 Datasheet, PDF (5/12 Pages) Catalyst Semiconductor – 128K/256K-Bit SPI Serial CMOS EEPROM

CAT25C128/256
FUNCTIONAL DESCRIPTION
The CAT25C128/256 supports the SPI bus data
transmission protocol. The synchronous Serial Peripheral
Interface (SPI) helps the CAT25C128/256 to interface
directly with many of today’s popular microcontrollers.
The CAT25C128/256 contains an 8-bit instruction
register. (The instruction set and the operation codes
are detailed in the instruction set table)
After the device is selected with CS going low, the first
byte will be received. The part is accessed via the SI pin,
with data being clocked in on the rising edge of SCK.
The first byte contains one of the six op-codes that define
the operation to be performed.
PIN DESCRIPTION
SI: Serial Input
SI is the serial data input pin. This pin is used to input all
opcodes, byte addresses, and data to be written to the
25C32/64. Input data is latched on the rising edge of the
serial clock.
SO: Serial Output
SO is the serial data output pin. This pin is used to transfer
data out of the CAT25C128/256. During a read cycle, data
is shifted out on the falling edge of the serial clock.
SCK: Serial Clock
SCK is the serial clock pin. This pin is used to synchronize
the communication between the microcontroller and the
CAT25C128/256. Opcodes, byte addresses, or data
present on the SI pin are latched on the rising edge of the
SCK. Data on the SO pin is updated on the falling edge of
the SCK.
CS: Chip Select
CS is the Chip select pin. CS low enables the CAT25C128/
256 and CS high disables the CAT25C128/256. CS high
takes the SO output pin to high impedance and forces the
devices into a Standby Mode (unless an internal write
operation is underway). The CAT25C128/256 draws
ZERO current in the Standby mode. A high to low transition
on CS is required prior to any sequence being initiated. A
low to high transition on CS after a valid write sequence is
what initiates an internal write cycle.
Figure 1. Sychronous Data Timing
V_IH
t_CS
CS
SCK
SI
V_IL
t_CSS
V_IH
V_IL
V_IH
VIL
t_WH
t_SU
t_H
VALID IN
V_OH
SO
V_OL
HI-Z
Note: Dashed Line= mode (1, 1) — — — —
t_CSH
t_WL
t_RI
tFI
t_V
t_HO
t_DIS
HI-Z
INSTRUCTION SET
Instruction
WREN
WRDI
RDSR
WRSR
READ
WRITE
Opcode
0000 0110
0000 0100
0000 0101
0000 0001
0000 0011
0000 0010
Operation
Enable Write Operations
Disable Write Operations
Read Status Register
Write Status Register
Read Data from Memory
Write Data to Memory
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Document No. 1018, Rev. I