CAT25C128_05 Datasheet, PDF (6/12 Pages) Catalyst Semiconductor – 128K/256K-Bit SPI Serial CMOS EEPROM

CAT25C128/256
WP: Write Protect
WP is the Write Protect pin. The Write Protect pin will
allow normal read/write operations when held high.
When WP is tied low and the WPEN bit in the status
register is set to “1”, all write operations to the status
register are inhibited. WP going low while CS is still low
will interrupt a write to the status register. If the internal
write cycle has already been initiated, WP going low will
have no effect on any write operation to the status
register. The WP pin function is blocked when the WPEN
bit is set to 0.
HOLD: Hold
The HOLD pin is used to pause transmission to the
CAT25C128/256 while in the middle of a serial sequence
without having to re-transmit entire sequence at a later
time. To pause, HOLD must be brought low while SCK is
low. The SO pin is in a high impedance state during the
time the part is paused, and transitions on the SI pins will
be ignored. To resume communication, HOLD is brought
high, while SCK is low. (HOLD should be held high any
time this function is not being used.) HOLD may be tied
high directly to V_cc or tied to V_cc through a resistor. Figure
STATUS REGISTER
7
6
5
4
WPEN
X
X
X
BLOCK PROTECTION BITS
9 illustrates hold timing sequence.
STATUS REGISTER
The Status Register indicates the status of the device.
The RDY (Ready) bit indicates whether the CAT25C128/
256 is busy with a write operation. When set to 1 a write
cycle is in progress and when set to 0 the device
indicates it is ready. This bit is read only.
The WEL (Write Enable) bit indicates the status of the
write enable latch . When set to 1, the device is in a Write
Enable state and when set to 0 the device is in a Write
Disable state. The WEL bit can only be set by the WREN
instruction and can be reset by the WRDI instruction.
The BP0 and BP1 (Block Protect) bits indicate which
blocks are currently protected. These bits are set by the
user issuing the WRSR instruction. The user is allowed
to protect quarter of the memory, half of the memory or
the entire memory by setting these bits. Once protected
the user may only read from the protected portion of the
array. These bits are non-volatile.
3
2
1
0
BP1
BP0
WEL
RDY
Status Register Bits
BP1
BP0
0
0
0
1
1
0
1
1
Array Address
Protected
None
25C128: 3000-3FFF
25C256: 6000-7FFF
25C128: 2000-3FFF
25C256: 4000-7FFF
25C128: 0000-3FFF
25C256: 0000-7FFF
Protection
No Protection
Quarter Array Protection
Half Array Protection
Full Array Protection
WRITE PROTECT ENABLE OPERATION
WPEN
0
0
1
1
X
X
WP
X
X
Low
Low
High
High
WEL
0
1
0
1
0
1
Protected
Blocks
Protected
Protected
Protected
Protected
Protected
Protected
Unprotected
Blocks
Protected
Writable
Protected
Writable
Protected
Writable
Status
Register
Protected
Writable
Protected
Protected
Protected
Writable
Document No. 1018, Rev. I
6