CAT25C128_05 Datasheet, PDF (10/12 Pages) Catalyst Semiconductor – 128K/256K-Bit SPI Serial CMOS EEPROM

CAT25C128/256
DESIGN CONSIDERATIONS
The CAT25C128/256 powers up in a write disable state
and in a low power standby mode. A WREN instruction
must be issued to perform any writes to the device after
power up. Also,on power up CS should be brought low
to enter a ready state and receive an instruction. After
a successful byte/page write or status register write the
CAT25C128/256 goes into a write disable mode. CS
must be set high after the proper number of clock cycles
to start an internal write cycle. Access to the array during
an internal write cycle is ignored and program-ming
is continued. On power up, SO is in a high impedance.
If an invalid op code is received, no data will be shifted
into the CAT25C128/256, and the serial output pin (SO)
will remain in a high impedence state until the falling
edge of CS is detected again.
When powering down, the supply should be taken down
to 0V, so that the CAT25C128/256 will be reset when
power is ramped back up. If this is not possible, then,
following a brown-out episode, the CAT25C128/256
can be reset by refreshing the contents of the Status
Register (See Application Note AN10).
Figure 9. HOLD Timing
CS
SCK
HOLD
SO
tCD
tHD
tHZ
Note: Dashed Line= mode (1, 1) — — — —
tCD
tHD
HIGH IMPEDANCE
tLZ
Figure 10. WP Timing
t_WPS
t_WPH
SCK
t_CSH
WP
Note: Dashed Line= mode (1, 1) — — — —
Document No. 1018, Rev. I
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