CAT34C02 Datasheet, PDF (6/17 Pages) Catalyst Semiconductor – 2-Kb I2C EEPROM for DDR2 DIMM Serial Presence Detect

CAT34C02
WRITE OPERATIONS
Byte Write
In Byte Write mode the Master sends a START, followed
by Slave address, byte address and data to be written
(Figure 5). The Slave acknowledges all 3 bytes, and the
Master then follows up with a STOP, which in turn starts
the internal Write operation (Figure 6). During internal
Write, the Slave will not acknowledge any Read or Write
request from the Master.
Page Write
The CAT34C02 contains 256 bytes of data, arranged
in 16 pages of 16 bytes each. A page is selected by the
4 most significant bits of the address byte following the
Slave address, while the 4 least significant bits point to
the byte within the page. Up to 16 bytes can be written
in one Write cycle (Figure 7).
The internal byte address counter is automatically in-
cremented after each data byte is loaded. If the Master
transmits more than 16 data bytes, then earlier bytes will
be overwritten by later bytes in a ‘wrap-around’ fashion
(within the selected page). The internal Write cycle starts
immediately following the STOP.
Acknowledge Polling
Acknowledge polling can be used to determine if the
CAT34C02 is busy writing or is ready to accept com-
mands. Polling is implemented by interrogating the
device with a ‘Selective Read’ command (see READ
OPERATIONS).
The CAT34C02 will not acknowledge the Slave address,
as long as internal Write is in progress.
Hardware Write Protection
With the WP pin held HIGH, the entire memory, as well
as the SWP flags are protected against Write operations
(Figure 8). If the WP pin is left floating or is grounded, it
has no impact on the operation of the CAT34C02.
Doc. No. 1095, Rev. C
6
© 2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice