CAT34C02 Datasheet, PDF (4/17 Pages) Catalyst Semiconductor – 2-Kb I2C EEPROM for DDR2 DIMM Serial Presence Detect

CAT34C02
PIN DESCRIPTION
SCL: The Serial Clock input pin accepts the Serial Clock
generated by the Master.
SDA: The Serial Data I/O pin receives input data and
transmits data stored in EEPROM. In transmit mode, this
pin is open drain. Data is acquired on the positive edge,
and is delivered on the negative edge of SCL.
A₀, A₁ and A₂: The Address pins accept the device ad-
dress. These pins have on-chip pull-down resistors.
WP: The Write Protect input pin inhibits all write op-
erations, when pulled HIGH. This pin has an on-chip
pull-down resistor.
FUNCTIONAL DESCRIPTION
The CAT34C02 supports the Inter-Integrated Circuit (I²C)
Bus data transmission protocol, which defines a device
that sends data to the bus as a transmitter and a device
receiving data as a receiver. Data flow is controlled by
a Master device, which generates the serial clock and
all START and STOP conditions. The CAT34C02 acts
as a Slave device. Master and Slave alternate as either
transmitter or receiver. Up to 8 devices may be connected
to the bus as determined by the device address inputs
A₀, A₁, and A₂.
I²C BUS PROTOCOL
The I²C bus consists of two ‘wires’, SCL and SDA. The
two wires are connected to the V_CC supply via pull-up
resistors. Master and Slave devices connect to the 2-
wire bus via their respective SCL and SDA pins. The
transmitting device pulls down the SDA line to ‘transmit’
a ‘0’ and releases it to ‘transmit’ a ‘1’.
Data transfer may be initiated only when the bus is not
busy (see A.C. Characteristics).
During data transfer, the SDA line must remain stable
while the SCL line is HIGH. An SDA transition while
SCL is HIGH will be interpreted as a START or STOP
condition (Figure 1).
START
The START condition precedes all commands. It consists
of a HIGH to LOW transition on SDA while SCL is HIGH.
The START acts as a ‘wake-up’ call to all receivers. Absent
a START, a Slave will not respond to commands.
STOP
The STOP condition completes all commands. It consists
of a LOW to HIGH transition on SDA while SCL is HIGH.
The STOP starts the internal Write cycle (when follow-
ing a Write command) or sends the Slave into standby
mode (when following a Read command).
Device Addressing
The Master initiates data transfer by creating a START
condition on the bus. The Master then broadcasts an
8-bit serial Slave address. The first 4 bits of the Slave
address are set to 1010, for normal Read/Write opera-
tions (Figure 2). The next 3 bits, A₂, A₁ and A₀, select
one of 8 possible Slave devices. The last bit, R/W,
specifies whether a Read (1) or Write (0) operation is
to be performed.
Acknowledge
After processing the Slave address, the Slave responds
with an acknowledge (ACK) by pulling down the SDA
line during the 9^th clock cycle (Figure 3). The Slave will
also acknowledge the byte address and every data
byte presented in Write mode. In Read mode the Slave
shifts out a data byte, and then releases the SDA line
during the 9^th clock cycle. If the Master acknowledges
the data, then the Slave continues transmitting. The
Master terminates the session by not acknowledging
the last data byte (NoACK) and by sending a STOP to
the Slave. Bus timing is illustrated in Figure 4.
Doc. No. 1095, Rev. C
4
© 2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice