CAT28F102 Datasheet, PDF (6/14 Pages) Catalyst Semiconductor – 1 Megabit CMOS Flash Memory

CAT28F102
A.C. CHARACTERISTICS, Program/Erase Operation
V_CC = +5V ±10%, unless otherwise specified.
JEDEC Standard
Symbol
tAVAV
Symbol
tWC
Parameter
Write Cycle Time
28F102-45 28F102-55
VCC = +5V ±5% VCC = +5V ±5%
Min. Max. Min. Max.
45
55
28F102-70 28F102-90
Min. Max. Min. Max.
70
90
Unit
ns
tAVWL
tAS
Address Setup Time
0
0
0
0
ns
tWLAX
tAH
Address Hold Time
30
30
35
40
ns
tDVWH
tDS
Data Setup Time
30
30
35
40
ns
tWHDX
tELWL
tWHEH
tWLWH
tWHWL
tWHWH1(2)
tWHWH2(2)
tDH
tCS
tCH
tWP
tWPH
-
-
Data Hold Time
10
CE Setup Time
0
CE Hold Time
0
WE Pulse Width
30
WE High Pulse Width 20
Program Pulse Width 10
Erase Pulse Width
9.5
10
10
10
ns
0
0
0
ns
0
0
0
ns
30
35
40
ns
20
20
20
ns
10
10
10
µs
9.5
9.5
9.5
ms
tWHGL
-
Write Recovery Time
6
Before Read
6
6
6
µs
tGHWL
-
Read Recovery Time
0
Before Write
0
0
0
µs
tVPEL
-
VPP Setup Time to CE 100
100
100
100
ns
Erase and Programming Performance ⁽¹⁾
28F102-45
28F102-55
28F102-70
28F102-90
Parameter
Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Unit
Chip Erase Time ⁽³⁾⁽⁵⁾
0.5 10
0.5 10
0.5 10
0.5 10 sec
Chip Program Time⁽³⁾⁽⁴⁾
1 6.5
1 6.5
1 6.5
1 6.5 sec
Note:
(1) Please refer to Supply characteristics for the value of V_PPH and V_PPL. The V_PP supply can be either hardwired or switched. If V_PP is
switched, V_PPL can be ground, less than V_CC + 2.0V or a no connect with a resistor tied to ground.
(2) Program and Erase operations are controlled by internal stop timers.
(3) ‘Typicals’ are not guaranteed, but based on characterization data. Data taken at 25°C, 12.0V V_PP.
(4) Minimum byte programming time (excluding system overhead) is 16 µs (10 µs program + 6 µs write recovery), while maximum is 400 µs/
byte (16 µs x 25 loops). Max chip programming time is specified lower than the worst case allowed by the programming algorithm since
most bytes program significantly faster than the worst case byte.
(5) Excludes 00H Programming prior to Erasure.
Doc. No. 25038-0A 2/98 F-1
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