CAT24WC33_05 Datasheet, PDF (6/12 Pages) Catalyst Semiconductor – 32K/64K-Bit I2C Serial CMOS EEPROM

CAT24WC33/65
WRITE OPERATIONS
Byte Write
If the Master transmits more than 32/64 bytes before sending
the STOP condition, the address counter ‘wraps around’,
and previously transmitted data will be overwritten.
In the Byte Write mode, the Master device sends the
START condition and the slave address information
(with the R/W bit set to zero) to the Slave device. After
the Slave generates an acknowledge, the Master sends
two 8-bit address words that are to be written into the
When all 32/64 bytes are received, and the STOP condi-
tion has been sent by the Master, the internal program-
ming cycle begins. At this point, all received data is written
to the CAT24WC33/65 in a single write cycle.
address pointers of the CAT24WC33/65. After receiving Acknowledge Polling
another acknowledge from the Slave, the Master device
transmits the data to be written into the addressed
memory location. The CAT24WC33/65 acknowledges
once more and the Master generates the STOP condi-
ts ^{tion. At this time, the device begins an internal program-}
ming cycle to nonvolatile memory. While the cycle is in
progress, the device will not respond to any request from
r _{the Master device.}
Page Write
a _{The CAT24WC33/65 writes up to 32/64 bytes of data,}
in a single write cycle, using the Page Write operation.
P _{CAT24WC33/65, Die Revision B = 32 Byte page.}
CAT24WC65, Die Revision D = 64 Byte page. The page
write operation is initiated in the same manner as the
d byte write operation, however instead of terminating
after the initial byte is transmitted, the Master is allowed
e ^{to send up to 31/63 additional bytes. After each byte has}
been transmitted, CAT24WC33/65 will respond with
an acknowledge, and internally increment the five
u _{low order address bits by one. The high order bits}
remain unchanged.
Disabling of the inputs can be used to take advantage of
the typical write cycle time. Once the stop condition is
issued to indicate the end of the host's write operation,
CAT24WC33/65 initiates the internal write cycle. ACK
polling can be initiated immediately. This involves issu-
ing the start condition followed by the slave address for
a write operation. If CAT24WC33/65 is still busy with the
write operation, no ACK will be returned. If
CAT24WC33/65 has completed the write operation, an
ACK will be returned and the host can then proceed with
the next read or write operation.
WRITE PROTECTION
The Write Protection feature allows the user to protect
against inadvertent programming of the memory array.
If the WP pin is tied to VCC, the bottom 1/4 of the memory
array (locations 000H to 7FFH for the 24WC65 and
locations 000H to 3FFH for 24WC33) is protected and
becomes read only. The CAT24WC33/65 will accept
both slave and byte addresses, but the memory location
tin ^{Figure 6. Byte Write Timing}
S
T
n BUS ACTIVITY: A SLAVE
MASTER ^R ADDRESS
T
BYTE ADDRESS
A15–A8
A7–A0
S
T
DATA
O
P
o SDA LINE _S
X XX _*
P
A
A
A
A
c_C
C
C
C
is ^K
K
K
K
24WC33/65 F08
D^{Figure 7. Page Write Timing}
S
T
BUS ACTIVITY: ^A SLAVE
MASTER ^R ADDRESS
T
BYTE ADDRESS
A15–A8
A7–A0
DATA
DATA n
S
T
DATA n+31
O
P
SDA LINE S
X XX _*
P
A
A
A
A
AA
A
C
C
C
C
CC
C
K
K
K
K
KK
K
* = Don't care bit for 24WC33
24WC33/65 F09
X= Don't care bit
Doc. No. 1049, Rev. D
6
© 2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice