CAT24WC33_05 Datasheet, PDF (5/12 Pages) Catalyst Semiconductor – 32K/64K-Bit I2C Serial CMOS EEPROM

CAT24WC33/65
I²C BUS PROTOCOL
compare to the hardwired input pins, A2, A1 and A0. The
The features of the I²C bus protocol are defined as
follows:
last bit of the slave address specifies whether a Read or
Write operation is to be performed. When this bit is set
to 1, a Read operation is selected, and when set to 0, a
(1) Data transfer may be initiated only when the bus is
Write operation is selected.
not busy.
After the Master sends a START condition and the slave
(2) During a data transfer, the data line must remain
stable whenever the clock line is high. Any changes
in the data line while the clock line is high will be
interpreted as a START or STOP condition.
START Condition
ts ^{The START Condition precedes all commands to the}
device, and is defined as a HIGH to LOW transition of
SDA when SCL is HIGH. The CAT24WC33/65 monitors
r _{the SDA and SCL lines and will not respond until this}
condition is met.
a _{STOP Condition}
A LOW to HIGH transition of SDA when SCL is HIGH
P _{determines the STOP condition. All operations must end}
with a STOP condition.
d _{DEVICE ADDRESSING}
e The bus Master begins a transmission by sending a
START condition. The Master sends the address of the
particular slave device it is requesting. The four most
u _{significant bits of the 8-bit slave address are fixed as}
1010 (Fig. 5). The next three bits (A2, A1, A0) are the
tin ^{device address bits; up to eight 32K/64K devices may}
to be connected to the same bus. These bits must
address byte, the CAT24WC33/65 monitors the bus and
responds with an acknowledge (on the SDA line) when
its address matches the transmitted slave address. The
CAT24WC33/65 then performs a Read or Write opera-
tion depending on the state of the R/W bit.
Acknowledge
After a successful data transfer, each receiving device is
required to generate an acknowledge. The Acknowledg-
ing device pulls down the SDA line during the ninth clock
cycle, signaling that it received the 8 bits of data.
The CAT24WC33/65 responds with an acknowledge
after receiving a START condition and its slave address.
If the device has been selected along with a write
operation, it responds with an acknowledge after receiv-
ing each 8-bit byte.
When the CAT24WC33/65 begins a READ mode it
transmits 8 bits of data, releases the SDA line, and
monitors the line for an acknowledge. Once it receives
this acknowledge, the CAT24WC33/65 will continue to
transmit data. If no acknowledge is sent by the Master,
the device terminates data transmission and waits for a
STOP condition. The master must then issue a stop
condition to return the CAT24WC33/65 to the standby
power mode and place the device in a known state.
n ^{Figure 4. Acknowledge Timing}
SCL FROM
1
o_MASTER
8
9
c_{DATA OUTPUT}
FROM TRANSMITTER
is_{DATA OUTPUT}
D ^{FROM RECEIVER}
START
ACKNOWLEDGE
5020 FHD F06
Figure 5. Slave Address Bits
1 0 1 0 A2 A1 A0 R/W
© 2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
5
5027 FHD F07
Doc No. 1049, Rev. D