CAT24WC33_05 Datasheet, PDF (3/12 Pages) Catalyst Semiconductor – 32K/64K-Bit I2C Serial CMOS EEPROM

CAT24WC33/65
A.C. CHARACTERISTICS
V_CC = +1.8V to +5.5V, unless otherwise specified
Output Load is 1 TTL Gate and 100pF
Read & Write Cycle Limits
CAT24WCXX-1.8
CAT24WCXX
1.8V-5.5V
2.5V-5.5V
4.5V-5.5V
Symbol Parameter
Min. Max. Min. Max. Min. Max. Units
F_SCL
T_I(1)
Clock Frequency
Noise Suppression Time Constant at
SCL, SDA Inputs
ts ^tAA
SCL Low to SDA Data Out and ACK
Out
r ^tBUF(1)
Time the Bus Must be Free Before
a New Transmission Can Start
4.7
t_HD:STA Start Condition Hold Time
4
a _tLOW
Clock Low Period
4.7
t_HIGH
Clock High Period
4
P _tSU:STA
Start Condition Setup Time
(for a Repeated Start Condition)
4.7
t_HD:DAT Data In Hold Time
0
d _{tSU:DAT Data In Setup Time}
50
e ^tR(1)
SDA and SCL Rise Time
t_F(1)
SDA and SCL Fall Time
u t_SU:STO Stop Condition Setup Time
4
t_DH
Data Out Hold Time
100
100
100
400 kHz
200
200
200 ns
3.5
3.5
1
µs
4.7
1.2
µs
4
0.6
µs
4.7
1.2
µs
4
0.6
µs
4.7
0.6
µs
0
0
ns
50
50
ns
1
1
0.3 µs
300
300
300 ns
4
0.6
µs
100
100
ns
tin _{Power-Up Timing (1)(2)}
Symbol
Parameter
n _tPUR
Power-Up to Read Operation
o _tPUW
Power-Up to Write Operation
Max.
1
1
c ^Note:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
(2) t_PUR and t_PUW are the delays required from the time V_CC is stable until the specified operation can be initiated.
Dis ^{Write Cycle Limits}
Units
ms
ms
Symbol
Parameter
Min.
Typ.
Max
Units
t_WR
Write Cycle Time
10
ms
The write cycle time is the time from a valid stop
condition of a write sequence to the end of the internal
program/erase cycle. During the write cycle, the bus
interface circuits are disabled, SDA is allowed to remain
high, and the device does not respond to its slave
address.
© 2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
3
Doc No. 1049, Rev. D