CAT24WC33_05 Datasheet, PDF (4/12 Pages) Catalyst Semiconductor – 32K/64K-Bit I2C Serial CMOS EEPROM

CAT24WC33/65
FUNCTIONAL DESCRIPTION
transfer all data into and out of the device. The SDA pin
The CAT24WC33/65 supports the I²C Bus data trans-
mission protocol. This Inter-Integrated Circuit Bus proto-
is an open drain output and can be wire-ORed with other
open drain or open collector outputs.
col defines any device that sends data to the bus to be ^{A0, A1, A2: Device Address Inputs}
a transmitter and any device receiving data to be a ^{These pins are hardwired or left unconnected (for hard-}
receiver. The transfer is controlled by the Master device ^{ware compatibility with CAT24WC16). When hardwired,}
which generates the serial clock and all START and ^{up to eight CAT24WC33/65s may be addressed on a}
STOP conditions for bus access. The CAT24WC33/65 ^{single bus system (refer to Device Addressing ). When}
operates as a Slave device. Both the Master device and ^{the pins are left unconnected, the default values are}
Slave device can operate as either transmitter or re-
ceiver, but the Master device controls which mode is
activated.
ts ^{PIN DESCRIPTIONS}
r ^{SCL: Serial Clock}
The serial clock input clocks all data transferred into or
a ^{out of the device.}
zeros.
WP: Write Protect
This input, when tied to GND, allows write operations to
the entire memory. For CAT24WC33/65 when this pin
is tied to Vcc, the bottom 1/4 array of memory (locations
000H to 7FFH for the 24WC65 and locations 000H to
3FFH for 24WC33) is write protected . When left floating,
memory is unprotected.
SDA: Serial Data/Address
P ^{The bidirectional serial data/address pin is used to}
Figure 1. Bus Timing
tF
tHIGH
tR
tLOW
tLOW
d _SCL
e _tSU:STA
tHD:DAT
tHD:STA
tSU:DAT
tSU:STO
u _{SDA IN}
tin ^{SDA OUT}
tAA
tDH
tBUF
n Figure 2. Write Cycle Timing
5020 FHD F03
SCL
Disco ^SDA
8TH BIT
BYTE n
ACK
tWR
STOP
CONDITION
START
CONDITION
ADDRESS
5020 FHD F04
Figure 3. Start/Stop Timing
SDA
SCL
Doc. No. 1049, Rev. D
START BIT
STOP BIT
5020 FHD F05
4
© 2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice