CAT24WC03_05 Datasheet, PDF (6/14 Pages) Catalyst Semiconductor – 2K/4K-Bit Serial EEPROM with Partial Array Write Protection

CAT24WC03/05
The CAT24WC03/05 responds with an acknowledge The CAT24WC03/05 writes up to 16 bytes of data in a
after receiving a START condition and its slave address. single write cycle, using the Page Write operation. The
If the device has been selected along with a write Page Write operation is initiated in the same manner as
operation, it responds with an acknowledge after receiving the Byte Write operation; however, instead of terminating
each 8-bit byte.
after the initial word is transmitted, the Master is allowed
to send up to 15 additional bytes. After each byte has
When the CAT24WC03/05 is in a READ mode it transmits
been transmitted, the CAT24WC03/05 will respond with
8 bits of data, releases the SDA line, and monitors the
an acknowledge and internally increment the low order
line for an acknowledge. Once it receives this
address bits by one. The high order bits remain
acknowledge, the CAT24WC03/05 will continue to
unchanged.
transmit data. If no acknowledge is sent by the Master,
the device terminates data transmission and waits for a
STOP condition.
ts ^{WRITE OPERATIONS}
r ^{Byte Write}
In the Byte Write mode, the Master device sends the
a ^{START condition and the slave address information}
(with the R/W bit set to zero) to the Slave device. After
the Slave generates an acknowledge, the Master sends
P _{the byte address that is to be written into the address}
pointer of the CAT24WC03/05. After receiving another
acknowledge from the Slave, the Master device transmits
d ^{the data byte to be written into the addressed memory}
location. The CAT24WC03/05 acknowledge once more
e ^{and the Master generates the STOP condition, at which}
time the device begins its internal programming cycle to
nonvolatile memory. While this internal cycle is in
u _{progress, the device will not respond to any request from}
the Master device.
tin ^{Page Write}
If the Master transmits more than 16 bytes prior to
sending the STOP condition, the address counter ‘wraps
around’, and previously transmitted data will be
overwritten.
Once all 16 bytes are received and the STOP condition
has been sent by the Master, the internal programming
cycle begins. At this point all received data is written to
the CAT24WC03/05 in a single write cycle.
Acknowledge Polling
The disabling of the inputs can be used to take advantage
of the typical write cycle time. Once the stop condition
is issued to indicate the end of the host’s write operation,
the CAT24WC03/05 initiates the internal write cycle.
ACK polling can be initiated immediately. This involves
issuing the start condition followed by the slave address
for a write operation. If the CAT24WC03/05 is still busy
with the write operation, no ACK will be returned. If the
CAT24WC03/05 has completed the write operation, an
ACK will be returned and the host can then proceed with
the next read or write operation.
Figure 6. Byte Write Timing
S
n^T
BUS ACTIVITY: ^A
MASTER ^R
T
o_{SDA LINE S}
SLAVE
ADDRESS
BYTE
ADDRESS
S
T
DATA
O
P
P
isc Figure 7. Page Write Timing
S
D^T
S
BUS ACTIVITY: ^A
SLAVE
BYTE
T
MASTER ^R ADDRESS
ADDRESS (n)
DATA n
DATA n+1
DATA n+P ^O
T
P
SDA LINE S
P
A
A
A
A
A
C
C
C
C
C
K
K
K
K
K
NOTE: IN THIS EXAMPLE n = XXXX 0000(B); X = 1 or 0
Doc. No. 1005, Rev. F
6
© 2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice