CAT24WC03_05 Datasheet, PDF (2/14 Pages) Catalyst Semiconductor – 2K/4K-Bit Serial EEPROM with Partial Array Write Protection

CAT24WC03/05
ABSOLUTE MAXIMUM RATINGS*
*COMMENT
Temperature Under Bias ................. –55°C to +125°C Stresses above those listed under “Absolute Maximum
Storage Temperature ....................... –65°C to +150°C
Voltage on Any Pin with
Respect to Ground⁽¹⁾ ........... –2.0V to +V_CC + 2.0V
VCC with Respect to Ground ............... –2.0V to +7.0V
Ratings” may cause permanent damage to the device.
These are stress ratings only, and functional operation of
the device at these or any other conditions outside of those
listed in the operational sections of this specification is not
implied. Exposure to any absolute maximum rating for
Package Power Dissipation
extended periods may affect device performance and
Capability (Ta = 25°C) .................................. 1.0W reliability.
Lead Soldering Temperature (10 secs) ............ 300°C
Output Short Circuit Current⁽²⁾ ........................ 100mA
ts ^{RELIABILITY CHARACTERISTICS}
Symbol
Parameter
r _NEND(3)
a ^TDR(3)
V_ZAP(3)
P _ILTH(3)(4)
Endurance
Data Retention
ESD Susceptibility
Latch-up
Min.
1,000,000
100
2000
100
Max.
Units
Cycles/Byte
Years
Volts
mA
d ^{D.C. OPERATING CHARACTERISTICS}
e ^{VCC = +1.8V to +5.5V, unless otherwise specified.}
Limits
Symbol
Parameter
Min
Typ
Max
u _{ICC Power Supply Current}
3
I_S(5)
Standby Current (V_CC = 5.0V)
0
tin ^ILI
Input Leakage Current
10
I_LO
Output Leakage Current
VIL
Input Low Voltage
–1
10
VCC x 0.3
n _VIH
Input High Voltage
VCC x 0.7
VCC + 0.5
o ^{VOL1 Output Low Voltage (VCC = 3.0V)}
0.4
V_OL2 Output Low Voltage (V_CC = 1.8V)
0.5
Units
mA
µA
µA
µA
V
V
V
V
Test Conditions
f_SCL = 100 kHz
V_IN = GND or V_CC
V_IN = GND to V_CC
V_OUT = GND to V_CC
I_OL = 3 mA
I_OL = 1.5 mA
isc ^{CAPACITANCE TA = 25°C, f = 1.0 MHz, VCC = 5V}
Symbol
Test
D^{CI/O(3) Input/Output Capacitance (SDA)}
Max
8
Units
pF
Conditions
VI/O = 0V
C_IN(3) Input Capacitance (A0, A1, A2, SCL, WP)
6
pF
V_IN = 0V
Note:
(1) The minimum DC input voltage is –0.5V. During transitions, inputs may undershoot to –2.0V for periods of less than 20 ns. Maximum DC
voltage on output pins is V_CC +0.5V, which may overshoot to V_CC + 2.0V for periods of less than 20ns.
(2) Output shorted for no more than one second. No more than one output shorted at a time.
(3) These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC-Q100
and JEDEC test methods.
(4) Latch-up protection is provided for stresses up to 100 mA on address and data pins from –1V to V_CC +1V.
(5) Standby Current (I_SB) = 0µA (<900nA).
Doc. No. 1005, Rev. F
2
© 2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice