CAT24WC03_05 Datasheet, PDF (3/14 Pages) Catalyst Semiconductor – 2K/4K-Bit Serial EEPROM with Partial Array Write Protection

CAT24WC03/05
A.C. CHARACTERISTICS
V_CC = +1.8V to +5.5V, unless otherwise specified.
Read & Write Cycle Limits
CAT24WCXX-1.8
CAT24WCXX
1.8V-5.5V
2.5V-5.5V
4.5V-5.5V
Symbol Parameter
Min. Max. Min. Max. Min. Max. Units
F_SCL
Clock Frequency
100
100
400 kHz
T_I(1)
Noise Suppression Time Constant at
SCL, SDA Inputs
ts ^tAA
SCL Low to SDA Data Out and ACK
Out
t_BUF(1)
Time the Bus Must be Free Before
a New Transmission Can Start
4.7
r _{tHD:STA Start Condition Hold Time}
4
a ^tLOW
Clock Low Period
4.7
t_HIGH
Clock High Period
4
P _tSU:STA
Start Condition Setup Time
(for a Repeated Start Condition)
4.7
t_HD:DAT Data In Hold Time
0
d ^tSU:DAT ^{Data In Setup Time}
50
t_R(1)
SDA and SCL Rise Time
e _tF(1)
SDA and SCL Fall Time
t_SU:STO Stop Condition Setup Time
4
u _tDH
Data Out Hold Time
100
200
200
200 ns
3.5
3.5
1
µs
4.7
1.2
µs
4
0.6
µs
4.7
1.2
µs
4
0.6
µs
4.7
0.6
µs
0
0
ns
50
50
ns
1
1
0.3 µs
300
300
300 ns
4
0.6
µs
100
100
ns
tin Power-Up Timing(1)(2)
Symbol
n tPUR
tPUW
Parameter
Power-up to Read Operation
Power-up to Write Operation
Max
Units
1
ms
1
ms
co Write Cycle Limits
Symbol
Parameter
Dis^tWR
Write Cycle Time
Min
Typ
Max
10
Units
ms
The write cycle time is the time from a valid stop interface circuits are disabled, SDA is allowed to remain
condition of a write sequence to the end of the internal high, and the device does not respond to its slave
program/erase cycle. During the write cycle, the bus address.
Note:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
(2) t_PUR and t_PUW are the delays required from the time V_CC is stable until the specified operation can be initiated.
© 2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
3
Doc. No. 1005, Rev. F