CAT24WC03_05 Datasheet, PDF (4/14 Pages) Catalyst Semiconductor – 2K/4K-Bit Serial EEPROM with Partial Array Write Protection

CAT24WC03/05
FUNCTIONAL DESCRIPTION
clock all data transfers into or out of the device. This is
The CAT24WC03/05 supports the I²C Bus data trans-
an input pin.
mission protocol. This Inter-Integrated Circuit Bus proto- ^{SDA: Serial Data/Address}
col defines any device that sends data to the bus to be ^{The CAT24WC03/05 bidirectional serial data/address}
a transmitter and any device receiving data to be a ^{pin is used to transfer data into and out of the device. The}
receiver. Data transfer is controlled by the Master device ^{SDA pin is an open drain output and can be wire-ORed}
which generates the serial clock and all START and ^{with other open drain or open collector outputs.}
STOP conditions for bus access. The CAT24WC03/05
operates as a Slave device. Both the Master and Slave
devices can operate as either transmitter or receiver, but
the Master device controls which mode is activated. A
maximum of 8 devices (24WC03) and 4 devices
(24WC05) may be connected to the bus as determined
ts ^{by the device address inputs A0, A1, and A2.}
r _{PIN DESCRIPTIONS}
a ^{SCL: Serial Clock}
The CAT24WC03/05 serial clock input pin is used to
P _{Figure 1. Bus Timing}
A0, A1, A2: Device Address Inputs
These inputs set device address when cascading mul-
tiple devices. When these pins are left floating the
default values are zeros.
A maximum of eight devices can be cascaded when
using the CAT24WC03. All three address pins are used
for CAT24WC03. If only one CAT24WC03 is addressed
on the bus, all three address pins (A0, A1, and A2) can
be left floating or connected to V_SS.
Discontinued ^{Figure2. WriteCycleTiming}
Figure 3. Start/Stop Timing
Doc. No. 1005, Rev. F
4
© 2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice