CAT24WC03_05 Datasheet, PDF (5/14 Pages) Catalyst Semiconductor – 2K/4K-Bit Serial EEPROM with Partial Array Write Protection

CAT24WC03/05
A total of four devices can be addressed on a single bus
when using the CAT24WC05 device. Only A1 and A2
address pins are used with this device. The A0 address
pin is a no connect pin and can be tied to V_SS or left
floating. If only one CAT24WC05 is being addressed on
the bus, the address pins (A1 and A2) can be left floating
or connected to V_SS.
STOP Condition
A LOW to HIGH transition of SDA when SCL is HIGH
determines the STOP condition. All operations must end
with a STOP condition.
DEVICE ADDRESSING
WP: Write Protect
The bus Master begins a transmission by sending a
If the WP pin is tied to VCC the upper half of memory array ^{START condition. The Master then sends the address}
becomes Write Protected (READ only)(locations 80H to
FFH for the CAT24WC03 and locations 100H to 1FFH
for the CAT24WC05). When the WP pin is tied to VSS or
left floating normal read/write operations are allowed to
ts ^{the device.}
r I²C BUS PROTOCOL
The following defines the features of the I²C bus protocol:
a _{(1) Data transfer may be initiated only when the bus is}
P ^{not busy.}
(2) During a data transfer, the data line must remain
stable whenever the clock line is high. Any changes
d in the data line while the clock line is high will be
interpreted as a START or STOP condition.
e _{START Condition}
The START Condition precedes all commands to the
u _{device, and is defined as a HIGH to LOW transition of}
SDA when SCL is HIGH. The CAT24WC03/05 monitor
tin ^{the SDA and SCL lines and will not respond until this}
condition is met.
Figure 4. Acknowledge Timing
n _{SCL FROM}
1
MASTER
of the particular slave device it is requesting. The four
most significant bits of the 8-bit slave address are fixed
as 1010 for the CAT24WC03/05 (see Fig. 5). The next
three significant bits (A2, A1, A0) are the device address
bits and define which device or which part of the device
the Master is accessing. Up to eight CAT24WC03 and
four CAT24WC05 can be individually addressed by the
system. The last bit of the slave address specifies
whether a Read or Write operation is to be performed.
When this bit is set to 1, a Read operation is selected,
and when set to 0, a Write operation is selected.
After the Master sends a START condition and the slave
address byte, the CAT24WC03/05 monitors the bus and
responds with an acknowledge (on the SDA line) when
its address matches the transmitted slave address. The
CAT24WC03/05 then performs a Read or Write operation
depending on the state of the R/W bit.
Acknowledge
After a successful data transfer, each receiving device is
required to generate an acknowledge. The
Acknowledging device pulls down the SDA line during
the ninth clock cycle, signaling that it received the 8 bits
of data.
8
9
o_{DATA OUTPUT}
c_{FROM TRANSMITTER}
is ^DATAOUTPUT
FROM RECEIVER
D ^START
ACKNOWLEDGE
Figure 5. Slave Address Bits
24WC03 _{1 0 1 0 A2 A1 A0 R/W}
24WC05 1 0 1 0 A2 A1 a8 R/W
* A0, A1 and A2 correspond to pin 1, pin 2 and pin 3 of the device.
** a8 corresponds to the address of the memory array address word.
***A0, A1 and A2 must compare to its corresponding hard wired input pins (pins 1, 2 and 3).
© 2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
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Doc. No. 1005, Rev. F