English
Language : 

CS42L51 Datasheet, PDF (82/83 Pages) Cirrus Logic – Low Power, Stereo CODEC with Headphone Amp
◁
CS42L51
15.REVISION HISTORY
Rev.
A1
A2
Date
May 2005
September 2005
Changes
Initial Release subject to legal notice.
Renamed pin 14, FILT1+, to DAC_FILT+ and pin 16, FILT2+, to ADC_FILT+.
Added 1.5 µF capacitor recommendation to figure “Typical Connection Diagram (Software Mode)”
on page 10.
Removed the 0.1µF capacitors from pins DAC_FILT+, ADC_FILT+ and VQ on the figures “Typical
Connection Diagram (Software Mode)” on page 10 and “Typical Connection Diagram (Hardware
Mode)” on page 11.
Added DAC Isolation specification to “Analog Input Characteristics (Commercial - CNZ)” on
page 13 and “Analog Input Characteristics (Automotive - DNZ)” on page 14.
Corrected specification table “Headphone Output Power Characteristics” on page 19.
Removed td timing specification from table in section “Switching Specifications - Serial Port” on
page 20.
Added ts(SDO-SK) and th(SK-SDO) timing specification to table in section “Switching Specifications -
Serial Port” on page 20.
Adjusted timing specifications ts(SD-SK) from 0 ns to 20 ns and th from 50 ns to 20 ns in table in sec-
tion “Switching Specifications - Serial Port” on page 20.
Added MIC Bias PSRR specification to “DC Electrical Characteristics” on page 24.
Adjusted specification table “Power Consumption” on page 25.
Removed QSM clock ratios 128, 192, 256, 384 and HSM ratios 128, 192 from Table 3 on page 37.
Modified Digital Mix description in section “Digital Mix (DIGMIX)” on page 50.
Corrected DAC Zero Cross timeout period in section “Zero Cross” on page 56.
Adjusted BEEP off time settings in section “Beep Off Time (OFFTIME[2:0])” on page 61.
Modified BEEP description in section “Beep (BEEP)” on page 62.
Adjusted the minimum settings for the “Noise Gate Boost (NG_BOOST) and Threshold
(THRESH[3:0])” on page 70.
Swapped bits PCMA_OVFL w/PCMB_OVFL and ADCA_OVFL w/ADCB_OVFL in register “Status
(Address 20h) (Read Only)” on page 71.
Corrected Charge Pump Frequency setting in section “Charge Pump Frequency
(CHRG_FREQ[3:0])” on page 71.
Added sections “Headphone THD+N versus Output Power Plots” on page 72 and “ADC_FILT+
Capacitor Effects on THD+N” on page 74.
82
DS679A2
 ▷