CS42L51 Datasheet, PDF (27/83 Pages) Cirrus Logic – Low Power, Stereo CODEC with Headphone Amp

CS42L51
4.2 Hardware Mode
A limited feature-set is available when the CODEC powers up in hardware mode (see “Recommended Power-Up
Sequence” on page 40) and may be controlled via stand-alone control pins. Table 2 shows a list of functions/fea-
tures, the default configuration and the associated stand-alone control available.
Hardware Mode Feature/Function Summary
Feature/Function
Default Configuration Stand-Alone Control
Note
Power Control
CODEC
PGAx
ADCx
DACx
MIC Bias
MICx Pre-amplifier
Powered Up
Powered Up
Powered Up
Powered Up
Powered Down
Powered Down
-
-
Auto Detect
Enabled
-
-
Speed Mode
Serial Port Slave Auto-Detect Speed Mode
-
-
Serial Port Master
Single-Speed Mode
MCLK Divide
(Selectable)
“MCLKDIV2” pin 2 ^{see Section 4.5}
on page 37
Serial Port Master / Slave Selection
Interface Control
ADC
DAC
(Selectable)
(Selectable)
“M/S” pin 29
“I²S/LJ” pin 3
see Section 4.5
on page 37
see Section 4.6
on page 39
ADC Volume & Gain
Digital Boost
Soft Ramp
Zero Cross
Invert
PGAx
Attenuator
ALC
Noise Gate
Disabled
Disabled
Disabled
Disabled
0 dB
0 dB
Disabled
Disabled
-
-
ADCx High-Pass Filter
Enabled
-
-
ADCx High-Pass Filter Freeze
Continuous DC Subtraction
Line/MIC Input Select
AIN1A to PGAA
-
-
AIN1B to PGAB
DAC Volume & Gain
HP Gain
AOUTx Volume
Invert
Soft Ramp
Zero Cross
Ramp
G = 0.6047
0 dB
Disabled
Enabled
Disabled
Disabled
-
-
DAC De-Emphasis
Signal Processing Engine (SPE)
MIX
Beep
Tone Control
Peak Detect & Limiter
(Selectable)
Disabled
Disabled
Disabled
Disabled
“DEM” pin 4
-
see Section
4.4.1 on page 33
-
Data Selection
Data Input (PCM) to DAC
-
-
Channel Mix
ADC ADCA = L; ADCB = R
-
-
DAC _{PCMA = L; PCMB = R}
Charge Pump Frequency
(64xFs)/7
-
-
Table 2. Hardware Mode Feature Summary
DS679A2
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