CS42L51 Datasheet, PDF (48/83 Pages) Cirrus Logic – Low Power, Stereo CODEC with Headphone Amp

CS42L51
Power Down PGA X (PDN_PGAX)
Default: 0
0 - Disable
1 - Enable
Function:
PGA channel x will either enter a power down or muted state when this bit is enabled. See note 1 on page
47.
This bit is used in conjunction with AINx_MUX bits to determine the analog input path to the ADC. Refer to
“ADCX Input Select Bits (AINX_MUX[1:0])” on page 53 for the required settings.
Power Down ADC X (PDN_ADCX)
Default: 0
0 - Disable
1 - Enable
Function:
ADC channel x will either enter a power down or muted state when this bit is enabled. See note 1 on page
47.
Power Down (PDN)
Default: 0
0 - Disable
1 - Enable
Function:
The entire CODEC will enter a low-power state when this function is enabled. The contents of the control
port registers are retained in this mode.
6.3 MIC Power Control & Speed Control (Address 03h)
7
AUTO
6
SPEED1
5
SPEED0
4
3-ST_SP
3
2
1
0
PDN_MICB PDN_MICA PDN_MICBIAS MCLKDIV2
Auto-Detect Speed Mode (AUTO)
Default: 1
0 - Disable
1 - Enable
Function:
Enables the auto-detect circuitry for detecting the speed mode of the CODEC when operating as a slave.
When AUTO is enabled, the MCLK/LRCK ratio must be implemented according to Table 3 on page 37. The
SPEED[1:0] bits are ignored when this bit is enabled. Speed is determined by the MCLK/LRCK ratio.
Speed Mode (SPEED[1:0])
Default: 01
11 - Quarter-Speed Mode (QSM) - 4 to 12.5 kHz sample rates
10 - Half-Speed Mode (HSM) - 12.5 to 25 kHz sample rates
01 - Single-Speed Mode (SSM) - 4 to 50 kHz sample rates
00 - Double-Speed Mode (DSM) - 50 to 100 kHz sample rates
Function:
Sets the appropriate speed mode for the CODEC in master or slave mode. QSM is optimized for 8 kHz sam-
ple rate and HSM is optimized for 16 kHz sample rate. These bits are ignored when the AUTO bit is enabled
(see Auto-Detect Speed Mode (AUTO) above).
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