CS42L51 Datasheet, PDF (23/83 Pages) Cirrus Logic – Low Power, Stereo CODEC with Headphone Amp

SWITCHING CHARACTERISTICS - SPI CONTROL PORT
(Inputs: Logic 0 = DGND, Logic 1 = VL)
Parameter
CCLK Clock Frequency
RESET Rising Edge to CS Falling
CS Falling to CCLK Edge
CS High Time Between Transmissions
CCLK Low Time
CCLK High Time
CDIN to CCLK Rising Setup Time
CCLK Rising to DATA Hold Time
Rise Time of CCLK and CDIN
Fall Time of CCLK and CDIN
(Note 19)
(Note 20)
(Note 20)
Symbol
f_sck
t_srs
t_css
t_csh
t_scl
t_sch
t_dsu
t_dh
t_r2
t_f2
Min
0
20
20
1.0
66
66
40
15
-
-
Notes:
19. Data must be held for sufficient time to bridge the transition time of CCLK.
20. For f_sck <1 MHz.
CS42L51
Max
6.0
-
-
-
-
-
-
-
100
100
Units
MHz
ns
ns
µs
ns
ns
ns
ns
ns
ns
RST
t_srs
CS
t_css
t_sch
t_scl
t_csh
t_r2
CCLK
t_f2
t_dsu t_dh
CDIN
Figure 8. Control Port Timing - SPI Format
DS679A2
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