CS42L51 Datasheet, PDF (21/83 Pages) Cirrus Logic – Low Power, Stereo CODEC with Headphone Amp

CS42L51
LRCK
SCLK
SDOUT
SDIN
t_s(LK-SK)
t_d(MSB)
t_s(SD-SK)
//
//
t_P
//
//
t_h(SK-SDO)
//
MSB
//
t_h
//
MSB
//
t_s(SDO-SK)
MSB-1
MSB-1
Figure 4. Serial Audio Interface Slave Mode Timing
Master Mode (Note 17)
Output Sample Rate (LRCK)
Parameters
LRCK Duty Cycle
SCLK Frequency
SCLK Duty Cycle
SCLK Rising Edge to SDOUT Output Delay
LRCK Edge to SDOUT MSB Output Delay
SDOUT Setup Time Before SCLK Rising Edge
SDOUT Hold Time After SCLK Rising Edge
SDIN Setup Time Before SCLK Rising Edge
SDIN Hold Time After SCLK Rising Edge
Symbol Min
All Speed Modes F_s
-
45
1/t_P
-
45
t_d
-
t_d(MSB)
-
t_s(SDO-SK)
30
t_h(SK-SDO)
30
t_s(SD-SK)
20
t_h
20
Max Units
M_------C_-----L_---K_---
Hz
128
55
%
64•F_s
Hz
55
%
--------1---------
s
MCLK
40
ns
-
ns
-
ns
-
ns
-
ns
Notes:
15. After powering up the CS42L51, RESET should be held low after the power supplies and clocks are set-
tled.
16. See “Example System Clock Frequencies” on page 75 for typical MCLK frequencies.
17. See “Master” on page 38.
LRCK
SCLK
SDOUT
SDIN
t_d(MSB)
t_s(SD-SK)
//
//
t_P
//
//
t_h(SK-SDO)
//
MSB
//
t_h
//
MSB
//
t_s(SDO-SK)
MSB-1
MSB-1
Figure 6. Serial Audio Interface Master Mode Timing
DS679A2
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