CS42526 Datasheet, PDF (61/90 Pages) Cirrus Logic – 114 dB, 192 kHz 6-Ch Codec with S/PDIF Receiver

CS42526
6.16 ADC Left Channel Gain (address 1Ch)
7
Reserved
6
Reserved
5
LGAIN5
4
LGAIN4
3
LGAIN3
2
LGAIN2
1
LGAIN1
0
LGAIN0
6.16.1 ADC LEFT CHANNEL GAIN (LGAINX)
Default = 00h
Function:
The level of the left analog channel can be adjusted in 1 dB increments as dictated by the Soft and
Zero Cross bits (SZC[1:0]) from +15 to -15 dB. Levels are decoded in two’s complement, as shown
in Table 17.
6.17 ADC Right Channel Gain (address 1Dh)
7
Reserved
6
Reserved
5
RGAIN5
4
RGAIN4
3
RGAIN3
2
RGAIN2
1
RGAIN1
0
RGAIN0
6.17.1 ADC RIGHT CHANNEL GAIN (RGAINX)
Default = 00h
Function:
The level of the right analog channel can be adjusted in 1 dB increments as dictated by the Soft and
Zero Cross bits (SZC[1:0]) from +15 to -15 dB. Levels are decoded in two’s complement, as shown
in Table 17.
Binary Code
001111
001010
000101
000000
111011
110110
110001
Decimal Value
+15
+10
+5
0
-5
-10
-15
Volume Setting
+15 dB
+10 dB
+5 dB
0 dB
-5 dB
-10 dB
-15 dB
Table 17. Example ADC Input Gain Settings
6.18 Receiver Mode Control (address 1Eh)
7
SP_SYNC
6
Reserved
5
DE-EMPH1
4
DE-EMPH0
3
INT1
2
INT0
1
HOLD1
0
HOLD0
6.18.1 SERIAL PORT SYNCHRONIZATION (SP_SYNC)
Default = 0
0 - CX & SAI Serial Port timings not in phase
1 - CX & SAI Serial Port timings are in phase
Function:
Forces the LRCK and SCLK from the CX & SAI Serial Ports to align and operate in phase. This func-
tion will operate when both ports are running at the same sample rate or when operating at different
sample rates.
DS585PP5
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